The documentation outlines the power up sequence. But there is no description or timing diagram showing the reset process. Ideally, we need a similar diagram for the reset process. Hence, the following questions:
1) To use the RESETZ to apply soft reset, what is signal transition level? So, we nned the inactive level (high or low) and active/asserted level
2) Is there a minimum pulse duration for applying RESETZ? If so, how much
3) When RESETZ is asserted/enabled, what other (INT_OUT, TIC_CONF_DONE, etc.) change state?
Mo
