PGA460: PGA460 Software Development Guide - SLAA730A - SCLK or TEST pin?

Jaatje

Part Number: PGA460

In the documentation (SLAA730A) it is stated that the SCLK pin has to be pulled high/low for the logic level communication in UART. However, in the PGA460 datasheet, it states the TEST pin has to be pulled high/low for the logic level communication.

Is this a mistake or is SCLK required to be pulled to 5v/3.3v for the correct logic level in UART?

over 5 years ago

0 Akeem Whitehead over 5 years ago

TI__Mastermind 27950 points

Jaatje,

If you are using UART communication, it is recommended (but not required) to pull SCLK to ground using a 10kOhm pull-down resistor.

The state of the TEST pin at device power-up determines the logic level of the UART interface. If TEST is floating or pulled-low during power-up, then the device uses 3.3V logic level UART. If the TEST pin is pulled-high with a 100kOhm (to either 3.3 or 5V) during power-up, then the device uses 5.0V logic level UART.

0 Jaatje over 5 years ago in reply to Akeem Whitehead

Prodigy 185 points

Ah great, was already sceptical when I read that in the documentation. Thanks!

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PGA460: PGA460 Software Development Guide - SLAA730A - SCLK or TEST pin?