Other Parts Discussed in Thread: PGA450Q1EVM
Are there any recommendations for OSC_SYNC_CTRL vs CLK_SEL setup scenario?
I've experienced some issues when OSC_SYNC_CTRL had other than programmed value - I noted the difference between what I wanted to set in OSC_SYNC_CTRL and what I've read from that register usign GUI in RESET. Only power off and reload firmware again fixed that.
I've seen it when running from development-ram - I'm not sure if it happens when running from OTP just because I did not have a possibility to do so many tests on OTP however I'm experiencing some rare issues when it leads me to the conclusion that behaviour may be similar.
What are restrictions - recomendations for setting up OSC_SYNC_CTRL?
I don't want to shift clock frequency - I'd like to use:
OSC_SYNC_CTRL=0x60;
CLK_SEL = 0x00; //internal clock
In mentioned failure situations I've read OSC_SYNC_CTRL to be 0x40 instead of 0x60.