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TMP112: write data hold time request

Part Number: TMP112

Hi Sir,

customer measured I2C AC timing and seen that  write data hold time of 1 bit before ACK was 49.82nS, which would not meet the specification of TMP112 SPEC greater than 100nS.

because only the first 1 bit of ACK will be seen, is there any risk?

because of the I2C write tHD of customer control IC, DATA wil be between 2560nS~2600nS, which will exceed the TMP112 specification of 900nS, will there be problem with this TMP112?

  • Tommy,

    It looks like customer is sending High Speed Mode command (see section 7.3.2.7 High-Speed (Hs) Mode) Can you confirm this is their intention?

    In HS Mode, the minimum hold time changes to 25ns, so 49.82ns meets this requirement.

    Minimum hold time must be met for correct operation. Maximum hold time does not negatively affect our device. Maximum hold time will change with SCL Frequency. Maximum hold time in the table was calculated for the maximum frequency shown in the spec table 6.6 Timing Requirements.

    Hold time of 2600ns is not a problem.

    thanks,

    ren

  • Hi Ren,

    thanks for yuor help and reply,

    the customer using standard-mode, and the clock is 100kHz.

    is there standard-mode specifiaction for datasheet table 6.6 ? thanks.

  • Hi Tommy,

    There isn't a problem using the HS Mode command with 100kHz communication as long as the HS Mode protocol is followed (no Stops.)

    If HS Mode is not being used, customer's 49ns does not meet minimum requirement of 100ns for Standard Mode. Usually this will cause the device to NACK during Address phase. 

    thanks,

    ren

  • Hi Ren,

    got it, may i know the following customer question are possible?

    because the write data hold time is 49ns, the point of occur is the bit before the ACK sent by TMP112, whether it is for TMP112 to send ACK early to cause this situation?

  • Hi Ren,

    customer use 100kHz clock communication , how do we know TMP112 in fast mode or High-speed mode?

  • Hi Tommy,

    High Speed mode is described in 7.3.2.7 High-Speed (Hs) Mode of the datasheet.

    thanks,

    ren

  • Hi Tommy,

    An I2C device must decide whether to ACK it's address during the 8th clock pulse. At the fall of the 8th clock, it will hold down SDA until the fall of the 9th clock to indicate ACK (shown in red.) Usually, hold time violation causes TMP112 to misread it's address during the first 8 clock pulses, so it will not ACK during the 9th pulse.

    thanks,

    ren