Other Parts Discussed in Thread: AWR1843
Hi,
I am working on designing a custom system to receive and relay ADC data available from the LVDS lanes on the AWR1843AOP chip to a PC through USB3.0 interface. I had a few questions relating to the LVDS and conversion specifications:
1) The maximum output data rate though LVDS has been specified to be 900Mbps (ref: AWR18xx/16xx/14xx Technical Reference Manual (Rev. E), section 15.3). I would like to read pure ADC data from the DFE continuously (by repeating a particular frame), without accompanying data (such as CP, CQ) at the highest speed possible (900Mbps). Given that all data from the CBUFF are received and transmitted with a 16-bit boundary, could I infer that, for the simple application described earlier, I would be reading 16bit data in interleaved format from both LVDS lanes at the rate of 56.25Mbps (900Mbps/16-bits)?
2) I am planning on using two deserializers (one for each LVDS lane) to convert serial data to parallel data. Since the data is structured around a 16-bit boundary, am I correct in assuming that if I used a 16-bit deserializer, I would have (with future updates) the flexibility with handling other output formats from the AWR1843AOP (expanding on the above simple application with added CP, CQ, user application data etc.)? Note that I would appropriately reprogram the data formatting used on the parallel data reader to combine and convert the 16-bit data.
3) Does the AWR1843AOP support both interleaved and non-interleaved data from the LVDS lanes?
4) Is the signal switching voltage of a single wire (not the differential voltage) of an LVDS lane 1.8V? (ref: AWR1843 Single-chip 77- and 79-GHz FMCW radar sensor datasheet, section 7.5)
