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AFE58JD16: SPI Register Problems and Decimation

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Part Number: AFE58JD16

Team,

Could you please answer my customer question,

  1. SPI-Register Readout fails
    The first Problem is that in certain constellations the SPI Readout of the AFE58JD16 fails. We were also able to reproduce this failure with the help of the TI-GUI. In the appendix you see some screenshots which show this behavior in detail.
    The problems is the readout of the DEMOD-register. When we do a readout of the register address 0x9C of the DEMOD register everything is fine and we get the expected value (0x8044). After that operation we read the ADC-register 0x03. If we want to read the DEMOD-register 0x9C again the readout “fails” and delivers 0xFFFF and not the value that is expected (0x8044).
    And idea what this failure is?

  2. Decimation and speed on the LVDS-Line
    We are using the AFE58JD16 with a 50MHz clock and we want to use the decimation (factor 4 or 5). We thought according to the display in the GUI (see the first image in the appended document) that ADC Output datarate is reduced by this factor. This is also the behavior of the ADS5294 which we used before. If the datarate would be reduced by the factor we expected the framerate at the FCLK-Pins would be 50MHz/4=12.5MHz. But the measured frequency is 50MHz! How can the AFE-IC be configured that only every fourth sample is transmitted over the LVDS-line? The highspeed of 50*16=800MHz would be too high for our FPGA? We do not want to do any Compression to use less LVDS lines, but we have to reduce the speed on all LVDS-lines.

The project is really time critical so hopefully you have a good solution for us, especially for the second problem.


Thank you.

Best,

Needhu

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    Regards

    Praveen

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