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IWR1642: Why changing SHMEMBANKSEL7TO4 doesn't make L3 remap work if I do it in SOC_deviceInit()?

Chris Meng
Mastermind 35215 points
Part Number: IWR1642

Test environment: IWR1642 ES2.0 EVM + mmWave SDK 2.0 

Hi,

I tried to modify the L3 mapping. I added the code to change the value of SHMEMBANKSEL7TO4 to 0x02010101 before SOC_mpu_config() in SOC_deviceInit(). But I found after rebuild the soc lib and the ccsdebug code and run, I still can't change the value of the extend TCMA address from 0x40000 to 0x5FFFF.

But if I changed the shared memory alloc for MulticoreImageGen.exe to 0x00000105, then I can change the value from from 0x40000 to 0x5FFFF. It seems ROM code change the value of SHMEMBANKSEL7TO4 and made the remap work.

Why changing SHMEMBANKSEL7TO4 doesn't make L3 remap work if I do it in SOC_deviceInit()? Is there any steps I must follow? Thanks.

  • 0
    TI__Mastermind 21295 points
    Hi Chris,

    I have requested more information from the software and design (bootloader) teams and will respond once I receive it.

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 21295 points
    Chris,

    After talking with the software team, it is recommended to set the shared memory allocation in the makefile during the build and not attempt to change the SHMEMBANKSEL7TO4 during runtime. Changing it during runtime can cause complications with the running software.

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 35215 points
    John,

    What’s the feedback on the question of post at e2e.ti.com/.../2704256
  • 0 in reply to Chris Meng
    TI__Mastermind 21295 points
    Hi Chris,

    If the goal/question is how to allocate all six L3 memory banks to DSP, then the recommended solution is to use the shared memory allocation in the makefile during the build and not attempt to change the SHMEMBANKSEL7TO4 during runtime. Is there a different goal you were trying to accomplish?

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 35215 points
    John,

    I understood that it is recommend to use makefile to change the L3 map.

    If you check the post at e2e.ti.com/.../2704256, you will find in that post I did use the makefile to change the L3 map. But I found the value of SHMEMBANKSEL7TO4 is not as expected as Bank 7 seems always to be mapped to BSS, no matter what I set in makefile.

    Would you pls check again?
  • 0 in reply to Chris Meng
    TI__Mastermind 21295 points
    Chris,

    Sorry, when I read your statement in this current thread "It seems ROM code change the value of SHMEMBANKSEL7TO4 and made the remap work" I thought that meant it was working for all your desired configurations. But it sounds like it is still not working as expected when you set shared memory alloc to 0x00000006 in the makefile. Please correct me if that is not accurate. Assuming that is the case I will try to reproduce the issue myself and then pursue it with the software team.

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 35215 points

    John,

    I set Shared memory alloc to 0x00000006 in makefile, rebuild the code, burn the qspi flash. After power on the board, I connect the CCS to view the value of SHMEMBANKSEL7TO4(address 0xFFFFE3CC) and found it is 0x10010101, instead of 0x01010101. Pls check at your side.

  • 0 in reply to Chris Meng
    TI__Mastermind 21295 points
    Chris,

    I will be able to allocate some time tomorrow to look at this.

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 21295 points
    Chris,

    I am seeing the same result you are seeing on my IWR1642BOOST ES2.0 EVM. It looks like bank 7 is always allocated to the RadarSS/BSS. I am checking with the bootloader team to find out why.

    Regards,
    John
  • 0 in reply to JohnH
    TI__Mastermind 21295 points

    Hi Chris,

    After communicating with the bootloader team, it looks like the "DSS_L3 Memory Organization for 16xx" section in the IWR16xx TRM will need to be updated to accurately reflect the L3 memory organization for IWR1642 ES2.0.  The updated L3 memory layout is shown in the following figure (each bank is 128KB).

    Therefore, only three of the shared L3 memory banks (3 x 128KB = 384KB) are available for allocation to the Master CR4F processor.  The DSP core can still use up to six banks for a total of 6 x 128KB = 768KB.

    Regards,

    John