AWR1243BOOST: AWR1243BOOST

yongzheng yang

Part Number: AWR1243BOOST
Other Parts Discussed in Thread: AWR1243

Hello,

I want to use FPGA to capture the RAW data of AWR1243 by LVDS ; I see the connection to the HD60 connector in AWR1243BOOST,

20 AR_LVDS_VALIDP
22 AR_LVDS_VALIDM

26 AR_LVDSSCSI_FRCLKP
28 AR_LVDSSCSI_FRCLKM

32 AR_LVDSSCSI_3P
34 AR_LVDSSCSI_3M

38 AR_LVDSSCSI_2P
40 AR_LVDSSCSI_2M

44 AR_LVDSSCSI_CLKP
46 AR_LVDSSCSI_CLKM

50 AR_LVDSSCSI_1P
52 AR_LVDSSCSI_1M

56 AR_LVDSSCSI_0P
58 AR_LVDSSCSI_0M

The questions is below:

1. What is the function of AR_LVDS_VALIDP/M and AR_LVDSSCSI_FRCLKP/M, is these signals used in LVDS or CSI2?

2. I want to use XILINX FPGA ISERDES to receive LVDS data, is there any fixed data for me to adjust the BITSLIP for correcting data?

Thanks very much.

over 4 years ago

0 Vivek Dham over 4 years ago

TI__Guru 58035 points

Hello,

The LVDS_VALID signal is high for the whole duration when valid LVDS data is available on the lines, but this signal is not mandatory to use.

The LVDS FRCLK signal provides one clk per ADC sample, you can refer to the AWr1243 datasheet to look at the timing. This signal in the FPGA can be used to align the valid data since it provides a sample boundary.

regards,

Vivek

0 yongzheng yang over 4 years ago in reply to Vivek Dham

Prodigy 160 points

Hi Vivek,

Thanks very much, but I can't find the LVDS_VALID and LVDS FRCLK signal in the AWr1243 datasheet , could you please take a screenshot of these two signal or show me which page can I find,

thanks.

0 Vivek Dham over 4 years ago in reply to yongzheng yang

TI__Guru 58035 points

Hello ,

Section 5.9.5 of the Awr1243 datasheet has the LVDS timing diagram. That does not show the LVDS_VALID ( only LVDS_FRCLK, LVDS_DATA, LVDS_CLK) , but like I said you don't really have to use the valid signal.

Regards,

Vivek

0 yongzheng yang over 4 years ago in reply to Vivek Dham

Prodigy 160 points

Thanks very much, my datasheet is too old, the new datasheet say that,

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AWR1243BOOST: AWR1243BOOST