AWR1443: scaling of PMIC_CLKOUT Frequency slope (register DCDCCTL0)

/* PMIC Clockout configuration */
typedef struct
{
    uint8      pmicClkOutEn;         /* PMIC clockout enable control. */
    uint8      pmicClkOutSrc;        /* PMIC clockout source clock.  */
    uint8      pmicClkSrcDiv;        /* Divide value to be applied to the source clock.*/
    uint8      modeSel;              /* Continuous mode or Chirp-chirp staircase mode*/
    uint32     freqSlope;            /* Frequency slope value to be applied in [8.18] format*/
    uint8      minNdivVal;           /* Min allowed divider value */
    uint8      maxNdivVal;           /* Max allowed divider value */
    uint8      clkDitherEn;          /* Clock dither enable */
    uint8      reservedMcu;          /* Reserved.  */

} pmicClockCfg_t;

/* Set the required value in this config */
pmicClockCfg_t pmicClkCfg;
/* Refer the ICD document for detail of each parameters [Sub block 0x4048] */
pmicClkCfg.pmicClkOutEn = 1;
pmicClkCfg.pmicClkOutSrc = 0; /* CLK Src XTAL: 40MHz */
pmicClkCfg.pmicClkSrcDiv = 250; /* 40M/250 = 160 KHz */
pmicClkCfg.modeSel = 0;
pmicClkCfg.freqSlope =0;
pmicClkCfg.minNdivVal = 249;
pmicClkCfg.maxNdivVal = 251;
pmicClkCfg.clkDitherEn = 0;

/* PMIC clockout enable request is issued*/
/* Disable the clock by gating off the clock */
toprcmREG->EXTCLKCTL[15:8] = 0xAD;

/* Setup the clock divider value */
toprcmREG->EXTCLKDIV[15:8] = pmicClkCfg.pmicClkSrcDiv;

/* Select the source of the PMIC clock */
toprcmREG->EXTCLKSRCSEL[11:8] = pmicClkCfg.pmicClkOutSrc;

/* Disable the dithering control block */
toprcmREG->DCDCCTL1[1] = 0U;
/* Setup the mode of operation */
toprcmREG->DCDCCTL1[8] = pmicClkCfg.modeSel;
/* Setup the divider value */
toprcmREG->DCDCCTL1[23:16] = pmicClkCfg.minNdivVal;
toprcmREG->DCDCCTL1[31:24] = pmicClkCfg.maxNdivVal;

/* Setup the frequency slope */
toprcmREG->DCDCCTL0[25:0]= pmicClkCfg.freqSlope;
/* Setup the clock dither control */
toprcmREG->DCDCCTL1[9] = pmicClkCfg.clkDitherEn;
/* Enable the dithering control block */
toprcmREG->DCDCCTL1[1] = 1U;
/* Ungate the PMIC clockout */
toprcmREG->EXTCLKCTL[15:8] = 0x0U;