TMP112-Q1: TMP112-Q1 : status of SDA/SCL pins during Power off (V+ =0V)

Akihisa Tamazaki

Part Number: TMP112-Q1

Hello team,

I have a question about TMP112-Q1 SDA/SCL pins during Power OFF (V+ =0V).

Do TMP112-Q1 SDA/SCL pins become Hi-Z at V+ =0V? If so, MCU can communicate with other I2C devices at same I2C line.
Would you please advise?

Best Regards,
Akihisa Tamazaki

over 4 years ago

0 Brandon Fisher94 over 4 years ago

TI__Mastermind 27645 points

Hello Akihisa,

Thank you for your post.

The SDA and SCL lines of the TMP112-Q1 are open drain, and will be High-z when the TMP112-Q1 is not powered. This means that the internal transistor is shut off and other devices on the bus can control the logic level to communicate.

Let me know if you have any other questions

Best Regards,
Brandon Fisher

0 Akihisa Tamazaki over 4 years ago in reply to Brandon Fisher94

TI__Genius 10905 points

Brandon-san,

I understand. Thank you so much.

Best Regards,
Akihisa Tamazaki

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TMP112-Q1: TMP112-Q1 : status of SDA/SCL pins during Power off (V+ =0V)