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AWR1843: Clearing Reset Cause with SPARE9 Register

Barend Ungrodt
Intellectual 1420 points
Part Number: AWR1843

Hi Radar Team,

My customer is attempting to write to the MSS_TOPRCM_SYSRSTCAUSECLR register to clear the reset cause. From previous discussions with them, they are aware that primary bootloader copies the reset cause to the SPARE9 register which is at address 0xFFFFE2FC, and through some experimenting found that writing 0 to that register seems to clear the reset. Is this an acceptable way to achieve his goal?

Thanks,
Barend

  • 0
    TI__Guru 69970 points

    Hi,

    Your assumption is right for SPARE9. Let me provide collective information here although most of this information is already available in TRM.

    SPARE9 Register is being written by the bootloader during its bootup sequence with corresponding reset cause value. 

    SPARE9 [27:20] =  previous MSS reset cause(mssRCM-> RSTCAUSE)    // 0xFFFFFFD8

    SPARE9 [19:16] =  previous system reset cause(topRCM->SYSRSTCAUSE) // 0xFFFFE124

    SPARE9 [11:4] = current MSS reset cause (mssRCM-> RSTCAUSE)

    SPARE9 [3:0] = current system reset cause (topRCM->SYSRSTCAUSE)

     

    And when bootloader loads application then post-loading it does ROM eclipse followed by R4F core reset, which will set mssRCM-> RSTCAUSE to 0x20 (CR4 reset because of Software trigger). So post application is up, you always see mssRCM-> RSTCAUSE as 0x20. You need to look for SPARE9 (0xFFFFE2FC) register for reset cause value which is set by bootloader (0x00990099 : System out of NRESET )

    Detail of individual registers which is being written to SPARE9 (can also be found in TRM)

    mssRCM->RSTCAUSE

    Gives cause of MSS reset
    0000_1001 : System out of NRESET 
    0000_1000 : Warm Reset
    0000_0010 : MSS only Wdog Reset.
    0000_0100 : MSS subsystem reset because of Software trigger.
    0010_0000 : CR4 reset because of Software trigger.
    0001_0000 : STC reset
    0100_0000 : CR4 reset because of writing to PRCR register in CR4 debug space.
    1000_0000 : CR4 only Wdog reset

    [It can be ORing of multiple event if event occurs]

    topRCM->RSTCAUSE

    Gives cause of chip reset
    “1001” : System out of NRESET
    “1010” : Warm reset because of MSS Wdog.
    “1100” : Warm reset because of Software trigger- SOFTSYSRST
    “1000” : External Warm Reset

    These two registers (topRCM->SYSRSTCAUSE & mssRCM-> RSTCAUSE) can be cleared by writing 0xAD value to MSS_TOPRCM_SYSRSTCAUSECLR (0xFFFF E128) and MSS_RCM_RSTCAUSECLR (0xFFFF FFDC)

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    TI__Intellectual 1420 points

    Hi Jitendra,

    Thanks for the detailed response! It's still not clear to me whether or not writing 0 to the register is an acceptable way to clear the reset. Are you saying instead of writing 0x0 to 0xFFFFE2FC, we should write 0xAD to both MSS_TOPRCM_SYSRSTCAUSECLR (0xFFFF E128) and MSS_RCM_RSTCAUSECLR (0xFFFF FFDC)?

    Thanks,
    Barend

  • 0 in reply to Barend Ungrodt
    TI__Guru 69970 points

    Hi Berend,

    To clear reset cause registers MSS_TOPRCM_SYSRSTCAUSECLR (0xFFFF E128) and MSS_RCM_RSTCAUSECLR (0xFFFF FFDC), you need to write 0xAD. If you need to clear SPARE9 (0xFFFFE2FC) register then you need to write 0.

    Regards,

    Jitendra