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AWR1843: AWR1843:How to configure DBS (default burst size) for EDMA ?

Prodigy 120 points

Replies: 13

Views: 171

Part Number: AWR1843

TRM has following description
12.2.12.5 EDMA_TPTC Configuration

Table 12-17 provides the configuration of the individual EDMA transfer controllers present on the device.
The DBS for each transfer controller is configurable using the EDMA_TPTCn_TCCFG register in the EDMA_TPTC modules.
And the Table 12-17. "EDMA Transfer Controller Configurations" also mentions DBS is configurable.
But I don't find any register for configure DBS.

Could you tell me which register is configured for DBS ?
Also, Could you tell me the address and specification of that register?

  • Guru 57545 points

    Hi,

    We need to check with design team and get back to you

    Cesar

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  • Hi, 

    For EDMA, we recommend to use the default reset value of DBS i.e. 64 bytes

    In case if you want to change it, may we know your use case? 

    Regards,

    Ishita

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  • In reply to Ishita Kochar:

    Table 12-16 "Read/Write Command Optimization Rules" mentions ACNT <= DBS is one condition of the Optimization Rules.
    so, I understand that a larger DBS allows for optimized transfer of larger data.
    Therefore I want to set DBS to 128 bytes.

    Regards.

  • In reply to user4810817:

    Hi,

    May I know the ACNT value that you're using for transfer?

    If you refer to the TRM document, ACNT <= DBS would be a condition for optimization only if a 2D-transfer is organized as a single transfer (i.e. continuous memory locations). The DBS size doesn't matter much in this case.You can just ensure that your ACNT value is less than or equal to 64 bytes. This would also lead to an optimized transfer.

    I hope I was able to answer to your query.

    Regards,

    Ishita

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  • In reply to Ishita Kochar:

    Hi,
    I want to use ACNT Value more than 64 bytes.

    For example,such as following
    Because the number of commands issued to the Read/Write controller changes,
    I understand that throughput will be affected by DBS setting.
    The pseudo code:
    1.DBS = 64,ACNT = 128, BCNT = 1023
        Read Controller/Write Controller
        Cmd0 = 64bytes
        Cmd1 = 64bytes
        ...
        Cmd2045 = 64bytes

    2.DBS = 128,ACNT = 128, BCNT = 1023
        Read Controller/Write Controller
        Cmd0 = 128bytes
        Cmd1 = 128bytes
        ...
        Cmd1022 = 128bytes

    So,could you tell me which register is configured for DBS ?

    Regards.

  • In reply to user4810817:

    Hi,

    I think there is an error in the TRM regarding this, thanks for pointing it out.

    We only support a fixed value of 64 bytes for DBS. You can only change your ACNT, BCNT values to optimize transfer. 

    Regards,

    Ishita

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  • In reply to Ishita Kochar:

    Hi, 

    I just wanted to confirm that you're not confusing burst size (DBS) with bus width. The throughput would be affected by the bus width and not the burst size (DBS). 

    The Bus matrix is of size 128 bits or 16 bytes. So maximum 16 bytes can be transferred per cycle and it would take 4 cycles to transfer 64 bytes (burst). If there is no other master who is requesting access to the same slave, the next burst would start immediately. Burst basically denotes the number of bytes(in cycles) that would be sent back to back.

    Burst size helps when there are multiple masters and a particular master shall be given more bandwidth as compared to other master to access a particular slave. The bus would not be released to other master until the complete burst is transferred. But in a non-arbitration mode(which means only one master), there shall be no or minimal impact between 64bytes and 128 bytes DBS.

    So I would want to know

    1. If you're using multiple masters, and

    2. What kind of transfer are you performing on the EDMA? This is just to understand the case where you're facing insufficient bandwidth. 

    Regards,

    Ishita

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  • In reply to Ishita Kochar:

    Hi,

    Thank you for the information.

    I have a deeper understanding of the DBS and buswidth.

    >1. If you're using multiple masters, and
    I use TPCC0 and TPCC1.
    TPCC0:assign ch0 to TC0, ch1 to TC1
    TPCC1:assign ch0 to TC2


    >2. What kind of transfer are you performing on the EDMA?
    I use TC0 for block move transfer of kBytes data.
    After TC0 transfer is complete,I use TC1 and TC2 in parallel for data sort transfer and block move transfer of kBytes data.
    Is there impact between 64bytes and 128 bytes DBS by my usage?

    Regards.

  • In reply to user4810817:

    Hi,

    If you refer to the following table in the TRM, it states that TC0 and TC1 have a FIFO size (512 bytes) higher than TC2 (128 bytes). 

    So while doing the parallel transfer in your case, TC2 will have a lower throughput. We suggest you to use either TC0 and TC1  or a combination of TC2 and TC3 to have the same throughput in both buses.

    Regards,

    Ishita

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  • In reply to Ishita Kochar:

    Hi,
    Thanks for the information.

    I would want to know

    1. I don't know much about FIFO width, how does it affect throughput?


    2. I'm currently useing SAM / DAM in increment mode.
    Is the FIFO width relevant only when I used SAM/DAM in FIFO mode?

    Regards

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