The following questions pertaint to reset and debug control of the DSS from the MSS side.
The application is running from internal SRAM and any reset or SOFTRESETREQ will rerun the bootloader
and overwrite the information he has downloaded to RAM with the contents from ext. flash.
We have addressed this by enabling ROM eclipsing and performing CR4 reset using the MSS_RCM:SOFTRST1 register.
The question here is if the VIM should be soft reset as well using the SOFTRST2 register?
The second question is on how to restart or control the DSP after a download to the DSP memories. The TRM under
27.2 mentions a Coresight cross trigger module CT-CTA to which the C674x megamodule is connected and which
according to the manual (see figure 27-3):
The second CTI module is present inside the debug subsystem. This CTI receives triggers from ADTF,
DMA, RTI, and WDT. GEM. The C674x DSP can be halted by any trigger in the subsystem. When GEM
trace is enabled, triggers are generated by ADTF by detecting the trigger packets in the trace stream.
However the manual does not state any specifics on this module and as it appears to be custom we would
need additional information on this module like component address, register map, functional description
etc. for CT-CTA component.
Can you elaborate on the CT_CTA component and the functionality of it?
What can the two triggers shown in the TRM do on the DSS side?
Alternatively is there a different way to soft reset the DSP from the CR4 side without rerunnig the bootloader?
Thank's in advance and Best Regards
Wolfgang Hoeld