TIDEP-01012: Device 2 : SPI Connection Failed

Hi Andreas, 

That message indicates to me that either: 

• AWR #1 master device is not configured or unable to supply the OSC_CLKOUT 40 MHz clock to the AWR #2 slave device
• The AWR#2 device did not come fully out of reset before SPI boot was attempted
• The AWR#2 device or host processor SPI traces/connector pins are damaged in some way

Were you running with the out of box lua script or a modified script?

Could you confirm if any of those issues are present? 

Are you mastering the MMWCAS-RF-EVM EVM from the MMWCAS-DSP-EVM? Or another host board? 

Thank you,

-Randy

Hello Randy,

thanks for your message.

1. We are utilising the TIDEP-01012 set consisting of MMWCAS-RF-EVM and MMWCAS-DSP-EVM.

2. We used a slightly modified lua script before, however we reinstalled mmwave Studio and use again the out of the box script.

3. I doubt that the SPI traces/connector pins would be damaged as we were very careful. (image below)

4. AWR #1 master device is not configured or unable to supply the OSC_CLKOUT 40 MHz clock to the AWR #2 slave device: How to test this?

5. The AWR#2 device did not come fully out of reset before SPI boot was attempted: How to test this?

Best, Andreas

Hello Randy,

is this maybe related to error: https://e2e.ti.com/support/sensors/f/1023/t/881829 (Reformating SSD - WARNING: rereading partition table failed,...)

Best,

Andreas

Hi Andreas, 

Is this system failing at this point consistently? Or do some initialization cycles continue correctly?

I do not think the issue in that other thread is directly related to that other thread, but I am curious why you needed to reformat the SSD. You should not have to do that out of the box. We just provide some convenient instructions in case you need to setup another SSD at some point. 

If you are configuring the device using the example MIMO Cascade\Cascade_Configuration_MIMO.lua you should be configuring the master and slave devices correctly unless there is a problem with the board. 

U7 is the 40 MHz clock fan-out buffer. You can probe at U7, pin 5, to observe the OSC_CLKOUT, 40 MHz clock being provided by the master device. You can observe the AWR #2 CLKP by probing the the via near the BGA entry point on the top layer. See below picture. Similar via probing locations are available for the other AWR #3 and AWR #4 devices. 

Thank you,

-Randy

Dear Randy,

it is failing at this point consistently and not only with the Cascade_Configuration_MIMO.lua script but also the other scripts provided. I also tried based on the GUI instruction to start it and it also did not work when I selected the devices 3 and 4 instead.

I will try to contact our technician to let him check the RF board and will come back to you in some time.

Regarding reformating the SSD: I thought I messed up something software-related after it did not start properly and so I tried to make a restart with installing everything clean (incl. firmware on the microSD).

Best, Andreas

Update regarding Error. When starting the board I observe different "failed" messages and at least one is related to the clock. Maybe this is helpful.

Load Kernel Modules

systemctl status systemd-modules-load.service

Synchronize System and HW clocks.

systemctl status sync-clocks.service

Network Service (Bus Name)

systemctl status org.networkd.service

systemctl status systemd-networkd.service

Synchronize System and HW clocks seems not to be the problem. Before leaving the office I wanted to restart the system and now it executed this part successfully without any error or warning.

Hi Andreas, 

Can you also please disconnect the RF and DSP boards from each other and check the host interface connectors on the RF board and the DSP board for any debris or anything that looks out of the ordinary?

Thank you,

-Randy