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BOOST-TUSS4470: SPI communication question

Kailyn Chen
Genius 9560 points

Part Number: BOOST-TUSS4470

Hello，

Our customer uses MSP-EXP430F5529LP and BOOST-TUSS4470 with SPI communication. The initial code is as following: 

    //Clock Polarity: The inactive state is high

    //MSB First, 8-bit, Master, 3-pin mode, Synchronous
    UCB0CTL1 |= UCSWRST;                      // **Put state machine in reset**
    UCB0CTL0 |= UCCKPL + UCMSB + UCMST + UCSYNC;
    UCB0CTL1 |= UCSSEL_2;                     // SMCLK
    UCB0BR0 |= 0x20;                          // /2
    UCB0BR1 = 0;                              //
    //UCA0MCTL = 0;                             // No modulation must be cleared for SPI

    //   SLAVE_CS_OUT &= ~SLAVE_CS_PIN;
    SLAVE_CS_OUT |= SLAVE_CS_PIN;
    UCB0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
    UCB0IE |= UCRXIE;                          // Enable USCI0 RX interrupt

The questions are：

1. Are there any  rules of 1 ODD parity bit for entire SPI frame?  If you could provide the examples about how to send 16bit data?

2. The BPF_CONFIG_1  address 0X10 is SPI address of SPI protocal? If you could give the read or write examples.

Best regards

Kailyn

  • 0
    TI__Mastermind 27950 points

    Hi Kailyn,

    Note, the SPI should be configured in SPI MODE 1, where the SDO line is sampled on the falling edge of the SCLK pin, and the SDI line is shifted out on the rising edge of the SCLK pin (CPOL=0, CPHA=1).

    Responding to the questions:

    1. Yes, the 1 ODD parity bit calculation applies to the entire 16-bit SPI frame. See below for examples:

    2. The BPF_CONFIG_1 address of 0x10 is for the device, but to perform a read example or write, consider these examples:

    Read: If the value at BPF_CONFIG_1 is 0x25, then the 16-bit SPI frame would be 0xA100, where 0xA1 is 10100001:

      • 1 = Read High / Write Low bit
      • 010000 = Register Address
      • 1 = ODD Parity bit


    In this case, there are only two bits set to '1' due to the read high bit and the register address, so the parity bit is set to '1' to create an odd number of '1' bits in the entire 16-bit frame.

    Write: If the value you want to write to BPF_CONFIG is 0x11, then the 16-bit MOSI SPI frame would be 0x2011, where 0x20 is 00100000:

      • 0 = Read High / Write Low bit
      • 010000 = Register Address
      • 0 = ODD Parity bit

    and 0x11 is the data byte. In this case there at already three (odd number) bits set to '1' due to the register address and the data byte, so the ODD parity bit remains '0'.

    We have an Energia library and code example package for the TUSS44x0 that will be available on TI.com this month to help show more examples.