Hi Keith,

Which pin mode you are using. 3-pin or 4-pin mode?

Thanks

Yogesh

What's the difference that affect the behaviour of the spi_hist_intr.  4 pin is just with the chip select. 3 pin is without the chip select. Why it will  affect spi_host_intr

Hi Keith,

Yes, unless you are using multi-buffer mode in slave mode spi_host_intr is not used. Current SDK driver doesn't support this mode.

Please refer to code @C:\ti\mmwave_sdk_03_03_00_03\packages\ti\drivers\spi for more details.

You can also reference section 23 @http://www.ti.com/cn/lit/ug/swru522d/swru522d.pdf 

Thanks

Yogesh

Did you mean Multi-Buffer RAM  ?
I believe the driver is support that by enable SPI_MULT_ICOUNT_SUPPORT.
I did not found the TRM describe anything about SPI_HOST_INTR nor anything in the driver/spi files when SPI_MULT_ICOUNT_SUPPORT is enabled .

I know the csHold can be enabled. But  can I still transfer at max 40Mhz in spi slave mode 4 pin ?
Most chipset does not support toggle cs for every word transfer.

Hi Keith,

Please read the note 2 for the SPI slave in 4-pin mode for multi RAM buffer. You may use external handshake b'n master and slave to achieve this.

With csHold enable the highest working SPI clock is 2MHz. See the SPI-PC test code @C:\ti\mmwave_sdk_03_03_00_03\packages\ti\drivers\spi\test

SPI transfer with multiple RAM buffer (icount)

SPI hardware has an internal RAM buffer that stores transmit/receive data element in 8bits or 16bits. The SPI driver has a compile time option to transfer data bigger than RAM buffer size. This is intended for high throughput transfers. But it has some limitations and not supported in all SPI modes.

Note1: There will be gaps between every transfer of the RAM buffer size for internal DMA copy of the data. During this time, Clock and CS will be inactive.

Note2: Slave needs time to do DMA copy of received data for every RAM buffer. Hence require the SPI master to deactivate CS/ClK signal during this time. When using another XWR1xxx device as master, it can be achieved by setting C2Tdelay/T2Cdelay/wdelay.

I do read all document and source code before posting questions.

It did not answer my question regarding the function of SPI_HOST_INTR pin when not acted as gpio_12  pin, but as SPI_HOST_INTR .
And regarding the 2MHz spi bus with csHold. Did  even  try it , or just based on the comment in that source code ?

From what I tried, it runs up to 15MHz without problem with csHold equals to one. Though I did not try 30Mhz which is the maximum of the FTDI chipset. Although IWR supports 40MHz.

Also I notice a bug in the spi driver that it output 128 bytes more than necessary.
I need to change the iCount+1 to iCount in order for spi_transfer function to return after the correct number of bytes are transferred. 
Would u pls confirm that also.

/* Configuring dma control packets for writing to TX RAM */
MIBSPI_sysDmaSetChanParams(ptrMibSpiDriver,
dmaChanTx,
(uint32_t)&ptrMibSpiDriver->txScratchBuffer,
txRAMAddr,
(uint16_t)(bufId + 1U),
(uint16_t)iCount + 1U,
MIBSPI_TRANSFER_DUMMY_TX);

/* Configuring dma control packets for reading from RX RAM */
MIBSPI_sysDmaSetChanParams(ptrMibSpiDriver,
dmaChanRx,
rxRAMAddr,
(uint32_t)(dstData),
(uint16_t)(bufId + 1U),
(uint16_t)iCount + 1U,
MIBSPI_TRANSFER_RX);

Hi Keith,

Please give me couple of days to get back.

Thanks, 

Yogesh