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LM94022: Output SAR

Guru 48045 points

Replies: 16

Views: 166

Part Number: LM94022

Hello,

Have 2 temp sensors monitor 2 heat sinks on 20Khz PWM system. One sensor is very quite direct coupled to ADC channel input no decoupling is required. The other sensor is very unstable no matter what ADC over sample or hold time, adding any amount decoupling cap 12pf<1.1nf makes temp roaming worse. The only way to settle it's output down was to add 2k pull down, sink/source current 1.67mA, far from 50µA. The VDD, GS0, GS1 trace now has 3.3µF>0.1uf ceramic and still required the 2k pull down.

The part that makes no sense is both sensors share VDD (3v3) source a single VIA. Also tried new sensor and concerned 1.67mA sink/source to ground should not be required alters temp results. Can not get stable reading, temp +/-3°C roaming as PWM duty cycle nears 85%. Both sensors are within 1" of each other, 2" from ADC input and both located on top side of PCB.They share same 3v3 rail VIA of star net on opposite sides of PCB, the noisy VDD net is stubbed 10mm next to 3v3 rail bus and source VIA. The other sensor 1" away VDD net runs through analog ground plane, only real difference. Thanks for suggestions.

What is recommended to quiet noisy sensor make it's output more stable?

  • Dear GI - 

    Have you used a near field or capacitive probe to determine the frequency of the noise being induced on the line? Perhaps it would be a good idea here if you provided your schematic and layout, as you have already noticed, its not the sensor which is noisy, (since your other sensor works fine) but noise riding on the line of this sensors' output which may be in turn impacting your ADC measurement. if you know the frequency of the noise, then you can calculate the RC lowpass filter values that might be needed. 

     

    BR-

    Josh

  • Guru 48045 points

    In reply to Josh Wyatt:

    Hi Josh,

    Josh Wyatt
    if you know the frequency of the noise, then you can calculate the RC lowpass filter values that might be needed. 

    That has already been established 20Khz duty speed bleeds into VDD. Why supply noise on this one sensor established a load regulation value +/-1mV for 1.67mA sink/source to ground per Fig.9 Cload is Lc+Cload? Checking again pull downs were 2k on both outputs to equalize ambient readings for oversampling. Any value decoupling capacitor made readings roam much worse on either sensor.

    Perhaps a ferrite or resistor to VDD could help to isolate it better. I was looking for any electronic reason why a pull down appears to dump 20Khz noise to ground, how to justify it works.

    Why does external load resistor added to output reduce voltage roaming on both sensors but any added capacitor decoupling makes roaming even worse? 

    There also seems to be datasheet oddness EC show Lc=1100pF load Typical. Then Fig.14 shows <1100pF no need for series R, how is that possible if Lc=1100pF typical?  

  • In reply to Gl:

    Dear GI -

    Without seeing what you have created, the general comment or advice would be to use a low pass filter (series R and shunt C) to satisfy the filter need. For example, as to not overpower your ADC sampling cap and have -3dB cutoff around 20kHz, you could use 10k in series and 820pF shunt cap or 11k and 720pF. 

    BR-

    Josh

  • Hi Gl,

    Have you tried replacing the problematic device? If it wasn't damaged before, there is a good chance it is damaged now that you've exceeded its output rating by 30x. 

    thanks,

    ren

  • Guru 48045 points

    In reply to Ren Schackmann:

    Ren Schackmann
    Have you tried replacing the problematic device? I

    The absolute maximum +/-7mA output, so 2k load (1.6mA) has not exceeded any rating. The +/-50µA source/sink is the minimum load current to be expected from the output direct coupling to another device.

    This sensor was acquired from National Semiconductor and seems to make some odd claim output capacitance CL being 1100pF typical after startup. Such capacitance would really distort ADC sample hold and does not require even more added. Fig.14 can not be <1100pF if the output is already 1100pF by design.  So that makes no sense other than no series R is required by default if CL<1100F after startup.

    Again Fig.14 distorts electrical characteristic CL=1100pF as such infers we can add more capacitance without series R since Lc<1100pF to begin with. Seemingly Fig.14 infers the output load CL is no greater than 1100pF during 1.9ms startup period. That is not being well clarified by CL= 0 pF to 1100 pF and static Lc likely reduces after peak load current stabilizes. We do not want to add more capacitance on the output for any reason what so ever.

    Why would Fig.14 even exist other than to suggest the output is indeed <1100pF after 1.9ms startup period? 

    The better question is what is the stabilized output Lc and impedance after 1.9ms startup? The question is important as to VDD noise rejection and mitigation techniques datasheet does not even consider. The simple fact the output swing impedance stabilizes by adding sink/source load resistance to ground seems to confirm VDD noise enters the LM internal rail. Even more interesting is larger sample hold times would not be required unless the source impedance is already very high.

     

  • In reply to Gl:

    Dear GI - 

    Section 7.4 in the datasheet is not making a claim about the part having a C of 1100pF.

    This section is specifically saying that if there is a capacitive load there, it should not exceed 1100pF. 

    it is common practice to put a bulk cap in front of an ADC, hence the note about the 1100pF limit and and when noise exists, a low-pass RC filter would be prescribed, as previously mentioned. 

    BR-

    Josh

  • Guru 48045 points

    In reply to Josh Wyatt:

    HI Josh,

    It would seem this is PSRR issue with VDD rail has to much input noise from 3v3 LDO when 20Khz is present. Otherwise LM is very stable and accurate with 2K pull downs during idle state. Yet it is very evident both LM device outputs are being pushed higher to some (-) degree when VDD (3v3) rail has 20kHz riding on 3v3 DC. 

    Perhaps 3v3 LDO regulator (TPS735) PSRR 68db at 1kHz noise rejection could be easily updated to another TI device. What would be a better PSSR LDO with WSON6 footprint is the bigger question? 

  • Guru 48045 points

    In reply to Josh Wyatt:

    Josh Wyatt
    Section 7.4 in the datasheet is not making a claim about the part having a C of 1100pF.

    There is no section 7.4 in datasheet (SNIS140E –MAY 2006–REVISED JUNE 2013) when the PCB was being designed in 2015. Again the electrical section indicates CL=1100pF TYPICAL does not concur with Fig.14 and highly distorts any logical sense being made of when series Rs is required or not required. Electrical section CL=1100pF note should indicate the output load capacitance LM adds into the connected circuit. It certainly appears to be a nonfactual listing derived from Fig.14 stated as being Typical CL load capacitance. The LM actually exhibits much lower CL than 1100pF especially when CL=0 beginning of 1.9ms startup period.

    How can CL=1100pF be the typical output load if no added capacitance is ever added to the output?  What is the definition of most likely parametric norm? To me it means the production anticipated LC value and not the application of the device with added LC from Fig.14 or Fig.15 

    Point again is Fig.14 Cload can never be less than 1100pF as indicated being typical electrical section from a device perspective, not the application of it relative to Fig.14 or Fig.15.  Please investigate why Fig.14 suggest no series Rs is required when CL is <1100pF and oddly the exact amount shown as being the typical load. The electrical section should not include data derived from the application section of the datasheet, without a footnote indicator to relate the data was derived from the application section.   

  • In reply to Gl:

    Dear GI - 

    I went back and looked at all the releases of this datasheet - apparently what was lost in last update version (from E to F) was the use of the word max as it relates to this parameter, in the parametric table. The 1100pF is not a typical load, it is the max capacitive load the part can handle without a current limiting/decoupling resistor and this is the intent of the table on page 14 of the current version of the document (Rev F) and this table and  this section has been in the datasheet since release in 2005. 

    In 2005, 2007 (x2) releases of SNIS140, this was section 4 (Capacitive Loading) on page 10. In 2009, the format was changed (this version still has the word max on 1100pF loading in characteristics table), and the section #s were removed, but the content remained the same with Capacitive Loads section appearing on pages 13 and 14. In Feb of 2013, when Rev D of this document was released, max still appears in characteristics table for CL, and the content regarding the loading and series R still appears on page 13 and 14. In June of 2013, when Rev E was released, max still appears in datasheet for CL and content is same. The 2015 version Rev F, current version, is where I see the (max) was removed from the characteristics table for CL and formatting was changed to have section numbers again, section 7.4 of interest here, and this has same content still as well, which indicates this is max load that could be present without the resistor. The current sourcing ability (50uA) has never changed - this is the reason for the mention of the limit all along and the recommendation to add series resistor, (which is also makes a low pass filter as well)

    Rev E, that you commented directly on - does in fact still have the word (max) in the line item for CL. and you are right, there were no section #s, but that same content under discussion here is on pages 13 and 14. 

    I have zipped up all the revisions of the datasheets in case you want to double check that - The content and the table have always been there. We will get the word (max) added back to the CL line item, so as to avoid any more confusion on this topic - it is an omission that needs to be rectified in the current version.  

    /cfs-file/__key/communityserver-discussions-components-files/1023/LMP94022_5F00_Datasheets.zip

      

        

    BR-

    Josh

  • Guru 48045 points

    In reply to Gl:

    Gl
    What would be a better PSSR LDO with WSON6 footprint is the bigger question? 

    It appears newer LDO 3v3 regulators with 100kHz PSRR and Noise <µV/Hz do not have similar WSON6 of TPS735 or are older devices with other issues. So no better or newer TI device exists to improve LM94022 VDD input noise rejection, leaving SMD ferrites to do that. 

    There is some wiggle room for TPS735 NR 10nF capacitor <100nF may help but I won't hold my breath. Another solution would be to find less VDD noise prone LM temperature sensor. That being said the LM94022 datasheet leaves one bewildered with more questions than answers.

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