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Part Number: LM94022
Have 2 temp sensors monitor 2 heat sinks on 20Khz PWM system. One sensor is very quite direct coupled to ADC channel input no decoupling is required. The other sensor is very unstable no matter what ADC over sample or hold time, adding any amount decoupling cap 12pf<1.1nf makes temp roaming worse. The only way to settle it's output down was to add 2k pull down, sink/source current 1.67mA, far from 50µA. The VDD, GS0, GS1 trace now has 3.3µF>0.1uf ceramic and still required the 2k pull down.
The part that makes no sense is both sensors share VDD (3v3) source a single VIA. Also tried new sensor and concerned 1.67mA sink/source to ground should not be required alters temp results. Can not get stable reading, temp +/-3°C roaming as PWM duty cycle nears 85%. Both sensors are within 1" of each other, 2" from ADC input and both located on top side of PCB.They share same 3v3 rail VIA of star net on opposite sides of PCB, the noisy VDD net is stubbed 10mm next to 3v3 rail bus and source VIA. The other sensor 1" away VDD net runs through analog ground plane, only real difference. Thanks for suggestions.
What is recommended to quiet noisy sensor make it's output more stable?
In reply to Gl:
Dear GI -
I am not sure what you mean by the last comment - the design detail you keep bringing up is really more related to the ADC you are interfacing to and the board layout you have created. Its' (the ADCs') specifications and requirements are what need to be known before one jumps to a conclusion that a resistor is needed or not, as this will let you know what the capacitive load is (before the board trace, etc.).
If you want, you have the option of sending over a schematic that includes the ADC you are using and we can have a look see on what its internal sampling cap is, etc and help you calculate / figure out what is going on there. Be glad to help. If you don't want to post it here, send me an email at email@example.com
Will look at the power supply options, too - but really it is better for me not be guessing here - the schematic will tell me everything i think i need to start with. Layout can be looked at after that.
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In reply to Josh Wyatt:
Josh WyattThe 1100pF is not a typical load, it is the max capacitive load the part can handle without a current limiting/decoupling resistor and this is the intent of the table on page 14 of the current version of the document (Rev F) and this table and this section has been in the datasheet since release in 2005.
That would be an odd way to relate how the LM output capacitance loads the circuit via N/PFET output structure section 5. The word load in the English dictionary infers a weight is being added to something else, never does it mean how much weight the load can or must be. Even adding the word MAX does not justify how much output CL is inerrant by design. Even If the word MAX was added how can anyone determine when RS is required for Fig.14. Accepted standard is to show CL being added by the device with foot note as to how much CL makes N/PFET output become unstable or oscillate.
It seems adding Condition word DRIVE in electrical section could help Fig.14 mean total CL without RS being added. My feeble mind refused to grasp any kind of meaning in this idea being related as is.
Section 7.4.1: the LM94022/-Q1 can drive a capacitive load less than or equal to 1100 pF as shown in Figure 13.
Thanks this has been on my mind for some time!
Josh WyattIf you want, you have the option of sending over a schematic that includes the ADC you are using and we can have a look see on what its internal sampling cap is, etc and help you calculate / figure out what is going on there
12 bit SAR ADC embedded into the MCU with 20pF internal charge cap. Rs impedance relates to Sample Hold times for derived over sample rate as to the Rs impedance change expected on each channel without adding resistors.
Presently the channels sequencer 1 does 64 over samples, sample hold 0x6 gives an equivalent Rs series impedance (9.5k) for 727KSPS.
Below tested every hold time possible at the maximum over sample rate basically the same roaming issues occur. The roaming only slows down does not go away and sometimes the error is more than 3°C . Oddly the farthest sensor located away from +3v3 source is much less troublesome. Rather PM you the layout areas PDF but was going to cut the VDD trace into LM add in 600zohm ferrite. Oddly don't see TI engineers use ferrites in many TIDA 2 sided example PCB's and this one would be ? without them.
/* Increase step sample hold time of sample sequencer.
* @32Mhz: Nsh(4) =Tshn0x0 encoding, Rs250 Allowable Impedance, 2.0Msps
* @32Mhz: Nsh(8) =Tshn0x2 encoding, Rs500 Max, 1.6Msps
* @32Mhz: Nsh(16)=Tshn0x4 encoding, Rs3.5k Max, 1.143Msps
* @32Mhz: Nsh(32)=Tshn0x6 encoding, Rs9.5k Max, 727Ksps
* @32Mhz: Nsh(64)=Tshn0x8 encoding, Rs21.5k Max, 421Ksps
* @32Mhz: Nsh(128)=Tshn0xA encoding, Rs45.5k Max, 229Ksps
* @32Mhz: Nsh(256)=Tshn0xC encoding, Rs93.5k Max, 119Ksps */
HWREG(ADC1_BASE + ADC_O_SSTSH1) = 0x6666;
good suggestion from before, will add that to the request for adding back the (max) notation in the characteristic table.
do you have the MCU part # you are using?
The MCU is a Tm4c1294kcpdt. Notice longer sample hold times reduce the sampling frequency, slows down acquisition relative to expected Rs load impedance. Sadly I did not put any series resistor pads on the output figuring it was low impedance by design.
couple things here, based on your schematic that you PM'ed me - (thanks for that)
the ferrite beads you are using probably have zero effect at 20kHz. If you look at their characteristic impedance, they really don't start doing anything useful until about 100MHz. You could probably remove them and short across the pads or find a bead that does have performance at that freqency of operation.
the input to your 5VDC (from switcher (this is assumption) to 3.3VDC LDO probably needs a PI filter (perhaps with a shielded inductor) instead and if you want to use two or three 2.2uF instead of one 4.7uF on your C64, this would lower the overall ESR and decrease any ripple more effectively as well.
your ground references should all be the same. you have a symbol for analog ground on regulator and earth ground for the rest of the parts. if those are truly separated, you might want to reconsider that as it would only make a differential grounding scheme for your circuit, vs. want you really want.
you can probably get rid of the 3.3VDC zener on the output of the regulator - probably have leakage current where you don't want any.
RE: the ADC, referencing https://www.ti.com/lit/ds/symlink/tm4c1294kcpdt.pdf, its clear (from your snippet above) that you saw page 1057. But it seems that there might be some misunderstanding here. The tables directly below there list the max RS values allowed at the different conversion rates.
Pages 1859 and 1862, though, have the electrical characteristics of the ADC, RADC and CADC and RS are listed there. The LM94022 is low impedance output, so you should be able to directly connect it.
There is a handy app note here as well, in case you want to check that out: https://www.ti.com/lit/an/spma001a/spma001a.pdf
hope that gets you in the right direction.
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