Part Number: LM75A
Q1:I2C interface electrical characteristic, What is the maximum allowable rise time?
Q2:If SDA and SCL rise time is 3.2usec, is there a problem happen?(SCL frequency is 25kHz）
Is there any possibility of IC damage?
Q3:When I2C interface receive data,how long it will take from clock judge H to the data latch?
Q4:When I2C interface transmission data, how long it will take from clock judge H to the data output?
A1: Maximum rise time can be derived from bus frequency and the required setup time. Note that the timing must be measured at the Vih and Vil thresholds of 0.7*Vcc and 0.3*Vcc. The clock period in the LM75A datasheet should be 2.5us (400kHz) instead of 2.5ns.
A2: There is not a problem if the timing parameters in the datasheet are met. The IC won't be damaged by timing parameter violations.
A3 & A4: There isn't a direct spec for this propagation time. TI has determined the device has adequate time to perform this action if the specified timing parameters are met.
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In reply to Ren Schackmann:
Thank you for your reply.
According to your answers A1 & A2, LM75A take no damage and work correctly with the rising time of 3.2us and the clock period of 40us.
Because our 40us of the clock period is larger than the 2.5us of minimun rising time specification.
And the maximum rising time specification is not mention in the data sheet of LM75A.
The other specifications of I2C characteristics written in the data sheet are also met on the our equipment.
Is it corresct?
I have additional questions about SDA and SCL terminals of LM75A.
Is there hysteresis on SDA and SCL terminals of LM75A ?
I am concerned about through current form Vdd to GND caused by long rising time.
I think that through current from Vdd to GND will not flow if SDA and SCL terminals have hysteresis.
So, I want to konw that SDA and SCL terminals of LM75A have hysteresis or not.
In reply to user6285443:
Hi Takayuki Kato,
I suspect this device does have Schmitt trigger hysteresis on the inputs, but I will need to confirm with design.
In reply to David Vaseliou:
Please let me konw the results you confirmed.
Do ICs of TI use the same I/O core circuitry?
I also want to know if ADC128D818 also uses the same digital I/O circuit as LM75A.
Hi Takayuki Kato,
I cannot share that information because it is proprietary.
Does it mean that you can't tell me if I/O has hysteresis or not ?
You mean the clock period in the LM75A datasheet should be 2.5us, so the LM75A datasheet have mistake? In section 6.7 the SCL period is 2.5ns（min）.
In reply to user6376542:
Kato - san,
that is correct - it is a typo. a clock period of 2.5nSec is equal to 400MHz (as f = 1/t), which is not a valid I2C clock speed.
2.5uSec on the other hand is equal to 400kHz, which is a valid I2C clock speed.
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