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AWR1243: The problem of valid signal when using LVDS mode of awr1243 to transmit data

Part Number: AWR1243

Hi,

We need to send the data sampled by ADC in awr1243 to FPGA through LVDS. However, we did not find the timing description of the valid signal in the relevant documents. All we know is that the valid signal is pulled up when awr1243 starts sending data. So we have some questions about the valid signal. Here are our questions:

  1. Where can we find the timing relation of valid signal in LVDS?
  2. The transmitting antenna adopts the working mode of time division multiplexing. When we switch the transmit antenna, will the valid signal be pulled down?
  3. When a PRT ends, will the valid signal be pulled down? PRT here refers to the time taken by three transmitting antennas to transmit a chirp in turn.( The transmitting antenna adopts the working mode of time division multiplexing.)

The version of awr1243 we use is AWR1243 ES3.0.

We look forward to your reply! Thank you!

Regards,

YANG