Dear;
TDC7200 unable to mask 1st stop signal. By referring to the datasheet TDC7200 (Page 14, section 8.3.3.3), device TDC7200 is unable to mask 1st stop signals even though Clock Counter STOP mask value is set lower than Clock Counter Overflow value as stated in the datasheet.]
[Steps Needed to Recreate Problem:
Step to recreate the problem:
1. Provided CLOCK frequency: 15.625MHz
2. Configure TDC register setting:
i.CONFIG1 register write value: 0x13
ii.CONFIG2 register write value: 0xc4
** The rest TDC registers are set to its reset value as stated in datasheet.
3. By referring to CONFIG1 register setting, after START signal, 5 pulse stop signals will be sent. TDC will capture positive edge START signal and negative edge STOP signal.
4. Here's timing without any pulse masking:
i. pulse 1: 328ns
ii. pulse 2: 760ns
iii. pulse 3: 1.19us
iv. pulse 4: 1.62us
v. pulse 5: 2.06us
5. Here's the setting for the TDC MASK:
i.CLOCK_CNTR_STOP_MASK_H write value: 0x00
ii.CLOCK_CNTR_STOP_MASK_L write value: 0x0A
6. Here's timing after pulse masking:
i. pulse 1: infinity
ii. pulse 2: infinity
iii. pulse 3: infinity
iv. pulse 4: infinity
v. pulse 5: infinity
*** timing value return infinity due to TDC register CALIBRATION1 and CALIBRATION2 return 0 value.
Best regards
Kailyn
