Site support forum - Recent Threads

AM263P2: Expired AM263X-RESTRICTED-SECURITY site

Jongho Park — Fri, 02 Oct 2026 06:36:09 GMT

Part Number: AM263P2

Hello~

I am unable to access the AM263X-RESTRICTED-SECURITY site because access has expired.
I would like to request renewed access.
We are currently designing a project using the AM263P2 and require ongoing support.

TPSM83100: Solder profiles recommended for TPSM83100SIUR

Leonel Ortiz — Mon, 21 Sep 2026 20:00:59 GMT

Part Number: TPSM83100

Can you please confirm solder profiles recommended for TPSM83100SIUR:

Maximum Reflow Temperature (°C)

Reflow Solder Time (Sec)

Number of Reflow Cycle

TMUX6208: Recommended solder profiles

Leonel Ortiz — Mon, 21 Sep 2026 19:56:49 GMT

Part Number: TMUX6208

Can you please help me to confirm the solder profiles recommended for this component MPN: TMUX6208RUMR

Maximum Reflow Temperature (°C)?

Reflow Solder Time (Sec)?

Number of Reflow Cycle?

PMP41117: who is my TI Rep in ft wayne Indiana

jeff Underwood — Fri, 18 Sep 2026 19:43:45 GMT

Part Number: PMP41117

Your chat does not work. All your Ph numbers are defunct. Im not impressed

All I wanted to start with was "WHO IS MY REP")?

AM263P4: access not provided for safety manual, still pending.

ROSHMON ROY — Fri, 18 Sep 2026 10:46:15 GMT

Part Number: AM263P4

TPS62177: Need COC ROHS and COC REACH253 documents

Thanan Kumnerdgerd — Thu, 17 Sep 2026 07:15:03 GMT

Part Number: TPS62177

Kindly provide COC ROHS and COC REACH253 for below list.

TPS62177DQCR

TCA9554PWR

TLV803EA29DBZR

PMP41037: Request for PMP41037 design guide

sabarinathan mohan — Wed, 16 Sep 2026 13:13:53 GMT

Part Number: PMP41037

Hello TI team,
I am referring to the PMP41037 reference design and have reviewed the available design resources. However, I could not locate the detailed PMP41037 design guide.
Would it possible to obtain the PMP41037 design guide or the associated design documentation for this reference design?

AM261-SOM-EVM: [AM261x] Required SysConfig and OSPI register settings for Octal DDR PSRAM with PHY mode enabled

okawachi hiroshi — Mon, 14 Sep 2026 13:53:08 GMT

Part Number: AM261-SOM-EVM
Other Parts Discussed in Thread: SYSCONFIG

Hello TI Support Team,

I am using AM261x OSPI1 with an AP Memory APS12808L Octal DDR PSRAM for external SRAM expansion.

The PSRAM is accessed through the OSPI1 memory-mapped region starting at:

0xA0000000

I would like to enable OSPI PHY mode, DQS-based read capture, and Direct Access Controller mode.

Could you please provide the recommended SysConfig settings and OSPI register settings for this configuration?

The registers and fields I am currently reviewing are:

OSPI_FLASH_CFG_CONFIG_REG
PHY_MODE_ENABLE_FLD
PIPELINE_PHY_FLD
ENABLE_DTR_PROTOCOL_FLD
ENB_DIR_ACC_CTLR_FLD

OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG
DDR_EN_FLD

OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG
DQS_ENABLE_FLD
DDR_READ_DELAY_FLD

My questions are:

Which SysConfig option enables OSPI1 PHY mode for PSRAM?
Which of the above register fields must be enabled?
Is PHY calibration or DLL tuning required for Octal DDR PSRAM?
Can the existing OSPI NOR Flash PHY tuning procedure be used for PSRAM?
Is there an MCU+ SDK PSRAM example that uses PHY mode?

I also need to perform 8-bit memory-mapped writes:

volatile uint8_t *psram =
(volatile uint8_t *)0xA0000000U;

psram[0] = 0xAAU;

The APS12808L requires a minimum two-byte write transfer and uses DQS/DM to mask the byte that must not be updated.

Does the AM261x OSPI1 Direct Access Controller automatically convert an R5F 8-bit store into a two-byte PSRAM write with the appropriate DM value?

If not, what is the recommended method for updating a single byte in the PSRAM?

A known-good SysConfig file or an OSPI1 register dump would be very helpful.

Best regards,
Hiroshi Okawachi

LM2574: Need to know product shelf life criteria for many TI parts

Vinay Salunkhe — Wed, 09 Sep 2026 06:26:12 GMT

Part Number: LM2574

Need to know product shelf life criteria for many TI parts as below list

MPN

SN74LVC1G07DCKR

SN74LVC3G34DCTR

TPS54260DGQR

ISO1412BDWR

SN65HVD1786DR

ISOW7842DWER

LM2575SX-3.3/NOPB

SN74LVC1G17DCKR

LM809M3X-3.08/NOPB

LM224DR

SN6501DBVR

LM258DGKR

TMP1075DR

SN65HVD3082EDR

TPS3808G25DBVR

LP38693SDX-5.0/NOPB

SN65HVD11DR

TPS2553DBVR

TLV62130RGTR

UCC28700DBVR

TL331KDBVR

TL431AIDBVR

TPS3809K33DBVR

LMV324IPWR

MSP430F4784IPZR

TS3A44159PWR

MSP430F2013IPWR

SN74HC595PWR

SN74LVC1G08DCKR

LM1117IDTX-5.0/NOPB

SN74AHCT1G126DCKR

LM2901PWR

SN74LV4066APWR

LMC660AIMX/NOPB

SN74AC14PWR

SN74LVC3G14DCUR

SN74LVC2G14DCKR

LM2574MX-3.3/NOPB

LM258DR

LP2951ACMX/NOPB

LM239DR

LP2950-33LPRE3

TLV431BQDBVR

REF3130AIDBZRG4

REF3130AIDBZR

TLV3701IDBVR

CAHCT1G126QDCKRG4

SN74LV595APWR

LM2903PWR

TL431BQDBVR

LMV796MFX/NOPB

LP2985-50DBVR

TLC3702MDR

SN74LVC1G125DCKR

LM4040C30IDBZR

ISO3082DWR

SN65HVD1785DR

ISO1640DWR

TPS76333DBVR

SN74LVC2G74DCTR

LMV331QDBVRQ1

SN74LVC1G06DCKR

TPS23753APWR

TPS54160DGQRG4

TPS73033DBVR

TXS0108EPWR

TPS62420DRCR

SN74AUP1G14DCKR

SN74AUP1G97DCKR

TPS76150DBVR

TPS55010RTER

SN74LVC2G08DCUR

LM2841YMKX-ADJL/NOPB

TPS62150RGTR

LM94022QBIMGX/NOPB

SN74LV4051APWR

TPS3839L30DBZR

SN65MLVD204ADR

TL431BIDBZR

UCC28740DR

TS5A22362DGSR

LP2950-50LPRE3

SN74LV595ADR

SN74LVC541APWR

TPS54218RTER

OPA343NA/3KG4

DP83822IRHBR

UCC28722DBVR

ADS131A04IPBSR

TLC6C598QPWRQ1

TLV70233DBVR

TLC6C598PWR

SN74LV1T34DCKR

LM5020MM-1/NOPB

TLC6C598CQDRQ1

OPA2170AIDGKR

TPS70950DBVR

WL1837MODGIMOCR

ADS131M04IPWR

MCP6292IDGKR

TPS62933DRLR

TPD4E05U06DQAR

SN74LVC2G32DCUR

SN74LVC1G04DSFR

SN74LVC125APWR

SN74LVC1G11DSFR

SN74AVC4T245PWR

SN74LVC1G32DSFR

SN74LVC14APWR

MAX3222EIPWR

SN74LVC574APWR

LP5912Q3.3DRVRQ1

TMAG5273A2QDBVR

TPD3F303DQDR

RF430CL331HIPWR

MSP430FG6626IPZR

SN74HC151PWR

TLV2252AIDR

TLV73333PDBVR

LM76003RNPR

TPD4E001DBVR

TMUX1308QPWRQ1

TLV62568DRLR

TPD1E1B04DPYR

LM317LIDR

CSD17318Q2T

THVD1550DR

TLV71310PDBVR

TS3USB221RSER

BQ21040DBVR

TXS0104ERGYR

TLV9062IDGKR

ISOW1412BDFMR

TL431BQDBZR

SN65HVD3082EDGKR

ISO7231CDWR

LMV321IDBVR

AM2612: AM2612: Question Regarding the AM261x + PSRAM

Koide Yoshiki — Mon, 07 Sep 2026 06:09:45 GMT

Part Number: AM2612
Other Parts Discussed in Thread: AM261-SOM-EVM, TMDSHSECDOCK-AM263, MCU-PLUS-SDK-AM261X, SYSCONFIG, LP-AM261

Hi Everyone on the AM261x Support Team,
I would appreciate your assistance with a few questions regarding the validation and operational track record of the AM261x with PSRAM.

1: Question Regarding the Operational Performance of the AM261-SOM-EVM + OSPI PSRAM
Could you please let us know whether the following hardware configuration has been validated or tested by TI?

Hardware and Software Environment
Hardware:
- AM261x SOM to HSEC Adapter Board
- APS12808L-3OBMx OPI Xccela PSRAM
- AM261-SOM-EVM
- TMDSHSECDOCK-AM263
Software:
- MCU-PLUS-SDK-AM261X 26.00.00.06

We have listed our development environment in the “Hardware and Software Environment” section above.
Could you please let us know whether this hardware configuration has been validated?
If not, could you please advise which versions and hardware configurations have been confirmed to work?

2: Question about PSRAM Dummy Cycle Settings on the AM261x LaunchPad
I noticed that the PSRAM dummy cycle settings are different between the SysConfig configuration and the values programmed in psram_ospi.c.

	SysConfig(*1)	psram_ospi.c(*2)
PSRAM Read Dummy Cycles	7	8
PSRAM Write Dummy Cycles	3	4
PSRAM Command Dummy Cycles	5	4

(*1) C:\ti\mcu_plus_sdk_am261x_26_00_00_06\examples\drivers\boot\sbl_ospi_multicore_elf\am261x-som\r5fss0-0_nortos\example.syscfg
(*2) C:\ti\mcu_plus_sdk_am261x_26_00_00_06\source\board\ram\ospi\psram_ospi.c

Could you please clarify whether this configuration is expected to work correctly as provided in the reference software?
If so, could you also explain why the read and write dummy cycle values differ between the SysConfig settings and the values written to the PSRAM mode registers in psram_ospi.c?
I would like to understand whether this difference is intentional (for example, due to device-specific requirements or an offset in the register encoding) or whether the values should be aligned.

Regards,
Yoshiki.

TPS63900: TPS63900: 3.3-V output becomes unstable at 1.8-V input under light/heavy load

saivenkat b — Fri, 04 Sep 2026 06:32:21 GMT

Part Number: TPS63900

Hi TI team,

I am evaluating the TPS63900 buck-boost converter for a low-power embedded system and have observed an unexpected behavior when operating close to the minimum input voltage.

My requirement is to generate 3.3 V from an input range of approximately 1.8 V to 4.2 V.

I tested the TPS63900 with resistive loads under the following conditions:

At VIN = 1.8 V, the output initially rises to approximately 3.3 V, but then periodically loses regulation and drops to approximately 0.9 V before recovering.

The input current also changes significantly during this behavior. For example, with the 3.3 kohm load, I measured approximately 342 uA average input current, but this is clearly not consistent with delivering a continuous 3.3 V / 1 mA load, since the output is not continuously regulated.

I initially observed this on my custom PCB, but I also reproduced the same behavior using the TPS63900 EVM, which makes me think this may be related to operation at the minimum VIN rather than my PCB implementation.

A few questions:

Is this behavior expected when operating at VIN = 1.8 V and boosting to 3.3 V?
Is there a minimum VIN-to-VOUT ratio or maximum output power/current that should be considered for stable operation near the 1.8 V input limit?
Are there specific inductor, output capacitor, current-limit, or control-mode settings that TI recommends for this operating point?
Does the TPS63900 have any recommended operating margin above the 1.8 V minimum input when generating 3.3 V?
Is there a recommended method for determining the minimum VIN for stable 3.3 V regulation at a given load?

For reference, I am using the TPS63900 with the recommended external components from the datasheet/EVM and monitoring VIN, VOUT and input current with a DMM, oscilloscope and Nordic Power Profiler.

Any guidance on whether this is expected behavior and how to properly characterize the minimum operating voltage would be appreciated.

Thanks.

I have documented all the tests that I have done TPS63900 PCB validation

Below is my schematic and layout

This is captured when a 3.3k resistor is connected as a load and 1800mV is given as input and this is the measured voltage.

TPS63900: TPS63900

takut yamada — Thu, 03 Sep 2026 09:49:32 GMT

Part Number: TPS63900
Other Parts Discussed in Thread: LMP7721

TPS63900
TPS7A2030
LMP7721
MAX3223EIPWR
TPS7A2030

Are the products with the model numbers listed above recommended for new designs?

If not, could you please suggest some alternatives?

Please confirm.

TPS7H4003-SEP: Tube QTY

Adriana Guevara — Wed, 02 Sep 2026 22:07:16 GMT

Part Number: TPS7H4003-SEP

Hello,

I want to order TPS7H4003MDDWSEP. The PN carrier is a TUBE and a TUBE has 35 units. If I put QTY as 1 and I receiving a TUBE of 35 units and a TUBE with only 1 unit?

Thank you,

Adriana

TMS570LS0432: TMS570LS043x: Application crashes after modifying TI FEE driver to use flash address 0xF0202000

Sneha Dakhare — Wed, 02 Sep 2026 09:37:25 GMT

Part Number: TMS570LS0432

Hi Team,
I am using TMS570LS043x and want to store 1 byte of runtime data at flash address 0xF0202000.

To do this, I modified:

TI_Fee_Init()

TI_FeeInternal_GetVirtualSectorParameter()

TI_FeeInternal_WriteVirtualSectorHeader()

and changed the virtual sector address to 0xF0202000.

After these changes, the application crashes when TI_Fee_Init() is called.

Questions:

Can 0xF0202000 be used directly with the TI FEE driver?
Does it need to be a valid Virtual Sector start address?
Is modifying these internal FEE functions the wrong approach for storing a single byte?
Should I use the F021 Flash API instead of modifying the FEE driver?

The application works correctly before these modifications.

Any suggestions would be appreciated.

Thanks.

TPS2595: Country of Origin

Brady Petrillo — Tue, 01 Sep 2026 16:12:38 GMT

Part Number: TPS2595

I need to know country of origin for the following component: TPS259521DSGR

AM68A: AM68-SK: SLB9672 on MCU_SPI1 – tpm_tis_spi probe fails with error -110 (no SCLK on header)

Duc Nguyen — Mon, 24 Aug 2026 11:28:53 GMT

Part Number: AM68A
Other Parts Discussed in Thread: AM68,

We are connecting an Infineon OPTIGA TPM SLB9672 (SPI) to the AM68-SK 40-pin header via MCU_SPI1.

Kernel reports: tpm_tis_spi spi1.0: probe with driver tpm_tis_spi failed with error -110

There is no /dev/tpm0 / /dev/tpmrm0.

Hardware wiring (CS0 test)

TPM signal	Header pin	SoC (expected)
SCLK	23	MCU_SPI1_CLK (D26)
MOSI	19	MCU_SPI1_D0 (E24)
MISO	21	MCU_SPI1_D1 (C28)
CS#	24	MCU_SPI1_CS0 (C27)
VDD	17	3.3 V
GND	25	GND
RST#	13	MAIN GPIO0_36 (W24), held HIGH

We also tested CS2 (pin 26, reg = <2> → spi1.2) with the same -110.

Software

CONFIG_TCG_TPM=y, CONFIG_TCG_TIS_SPI=y (built-in)
Overlay enables &mcu_spi1, pinmux on &wkup_pmx2:
- CLK/MOSI/MISO: mux mode 0
- CS0: mux mode 0 (or CS2 mode 1 when testing CS2)
DT node example (CS0):

dts

/dts-v1/;
/plugin/;

#include "k3-pinctrl.h"
#include <dt-bindings/gpio/gpio.h>

&mcu_rpi_header_gpio0_pins0_default {
	pinctrl-single,pins = <
		J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* G25 */
		J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* G27 */
		J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* J26 */
		J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* J27 */
		J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/

	>;
};

&wkup_pmx2 {
	mcu_spi1_pins_default: mcu-spi1-default-pins {
		pinctrl-single,pins = <
			J721S2_WKUP_IOPAD(0x058, PIN_OUTPUT, 0) /* D26 CLK */
			J721S2_WKUP_IOPAD(0x05C, PIN_OUTPUT, 0) /* E24 MOSI */
			J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 0)  /* C28 MISO */
			J721S2_WKUP_IOPAD(0x064, PIN_OUTPUT, 0) /* C27 CS0 — OUTPUT mode 0 */
		>;
	};
};

&main_gpio0 {
	tpm_reset_hog {
		gpio-hog;
		gpios = <36 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "tpm-reset";
	};
};

&mcu_spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_spi1_pins_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	ti,spi-num-cs = <1>; 

	tpm@0 {
		compatible = "infineon,slb9672", "infineon,slb9670", "tcg,tpm_tis-spi";
		reg = <0>;             /* → spi1.0 */
		spi-max-frequency = <1000000>;
	};
};

Log:

root@am68a-sk:/opt/edgeai-gst-apps# uname -a
Linux am68a-sk 6.12.17-ti-00773-gcdcaeac783e3-dirty #1 SMP PREEMPT Thu Apr  3 17:42:36 UTC 2025 aarch64 GNU/Linux
root@am68a-sk:/opt/edgeai-gst-apps# zcat /proc/config.gz 2>/dev/null | grep -E 'CONFIG_TCG_TPM=|CONFIG_TCG_TIS_SPI=|CONFIG_SPI='
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_SPI=y
CONFIG_SPI=y
root@am68a-sk:/opt/edgeai-gst-apps# ls /sys/bus/spi/devices/
spi0.0  spi1.0
; echo
  cat /sys/firmware/devicetree/base/bus@100000/bus@28380000/spi@40310000/tpm@0/compatible 2>/dev/null | tr '\0' ' '; eroot@am68a-sk:/opt/edgeai-gst-apps#   cat /sys/firmware/devicetree/base/bus@100000/bus@28380o
okay
root@am68a-sk:/opt/edgeai-gst-apps#   cat /sys/firmware/devicetree/base/bus@100000/bus@28380000/spi@40310000/tpm@0/compatible 2>/dev/null | tr '\0' ' '; echo
infineon,slb9672 infineon,slb9670 tcg,tpm_tis-spi 
root@am68a-sk:/opt/edgeai-gst-apps#   hexdump -C /sys/firmware/devicetree/base/bus@100000/bus@28380000/spi@40310000/tpm@0/reg 2>/dev/null
00000000  00 00 00 00                                       |....|
00000004
root@am68a-sk:/opt/edgeai-gst-apps# cat /sys/kernel/debug/gpio | grep tpm-reset
 gpio-669 (                    |tpm-reset           ) out hi 
root@am68a-sk:/opt/edgeai-gst-apps# dmesg | grep -i tpm_tis_spi
[    8.236838] tpm_tis_spi spi1.0: probe with driver tpm_tis_spi failed with error -110
root@am68a-sk:/opt/edgeai-gst-apps#   ls -l /dev/tpm* 2>/dev/null || echo "NO /dev/tpm*"
NO /dev/tpm*

What already works

/sys/bus/spi/devices/spi1.0 exists
spi@40310000 status = okay
Live DT: correct compatible and reg
RST GPIO hog shows out hi (tpm-reset)
Decompiled overlay shows expected pad offsets for CLK/MOSI/MISO/CS0

What fails

Probe always timeout (-110)
On scope/logic analyzer, we do not see SCLK (and related SPI activity) on header pin 23 during unbind/bind of tpm_tis_spi

Questions for TI

For AM68-SK, is MCU_SPI1 on the 40-pin header the correct interface for an external SPI TPM, and are the pinmux modes above correct for CS0 (and CS2)?
Any known requirement so that McSPI actually toggles CLK/CS on these pads when tpm_tis_spi probes (extra DT flags, power domains, clocks)?
Could our overlay on &mcu_rpi_header_gpio0_pins0_default (removing SPI pins from the GPIO group) still leave pads in a state where SPI signals never reach the header?
Recommended way to confirm at runtime that 40310000.spi pinmux is applied to the header pins?
Any TI reference DT or app note for SPI slave on MCU_SPI1 (CS0/CS2) on AM68-SK?

Thanks.

TIDA-010089: Altium Design files for this reference design

Ethan Della-Negra — Fri, 21 Aug 2026 08:48:47 GMT

Part Number: TIDA-010089

Hello TI Support,

I am modifying the TIDA-010089 reference design to integrate a custom MCU for the DAC.

Could you please provide the native Altium Designer source files (schematic and PCB layout) for this design? If you need to send them via a private channel, please let me know how to proceed.

Thank you, Ethan

SN74AVC4T774: PCN - SN74AVC4T774PWR

Nitin Gond — Tue, 18 Aug 2026 06:35:25 GMT

Part Number: SN74AVC4T774

Hi Team,

We have recived the folllowing PCN for the below part : SN74AVC4T774PWR

Could you please confirm is this PCN will impact on Fit, form and function.

PCN20260409005.1A.pdf

Thanks,

Nitin Gond.

LMR38010-Q1: DC-DC IC Failed

Gobi Rajagopal — Thu, 06 Aug 2026 09:04:18 GMT

Part Number: LMR38010-Q1

LMR38010FSQDDARQ1 Failure Observation

We observed failure (short circuit) of two LMR38010FSQDDARQ1 devices.

Initially, the EN pin was directly connected to the VIN pin, and the circuit operated without any issues.

Later, a Common Mode Choke (CMC) was added in the input line to improve EMI/EMC performance, and the EN pin was connected to the Ignition (IGN) input instead of the IN pin. Following this change, the LMR38010FSQDDARQ1 devices started failing and became short-circuited.

Subsequently, 47 k series resistor was added in the EN pin path, after which the circuit has been operating reliably without any failures.

Could you help identify the possible root cause of this failure?

According to the datasheet, the EN pin can withstand voltages greater than 80 V, whereas our system input voltage is only 24 V, our total load current is 60mA and DC-DC output is 13V (24V to 13V), 400KHZ SW freq

TPS51397A: Package details

Ritika Saluja — Thu, 06 Aug 2026 02:47:48 GMT

Part Number: TPS51397A

Hi,

No package information available in datasheet:TPS51397A 4.5-V to 24-V, 10-A Synchronous Buck Converter with ULQ™ Operation datasheet (Rev. A)

Also, please confirm either RJE0020B or RJE0020A is right package to use for this part?

Regards,

Ritika Saluja

AM625: AM625 MPU selection reference with display support on native Android kernel

madhu h — Tue, 04 Aug 2026 05:17:49 GMT

Part Number: AM625

hello customer support,

Looking for AM625x processor or equ. that is capable of handing hi speed communication using CAN, has display interfaces and can run on Android OS. Please suggest me the right processor on performance, at the same time would like to get an eval kit on par with this.

Request to connect with me.

TXS0102-Q1: Shelf-life data sheet needed

Benjamin Pal — Thu, 23 Jul 2026 10:36:46 GMT

Part Number: TXS0102-Q1

Hello TI Team,

We would need urgently a data sheet regarding to TXS0102QDCURQ1 which confirm the accurate shelf-life time of the material.

Thanks.

Br,

Benjamin

BQ41Z90EVM: BQ41Z90EVM u1 IC

林春盛 — Wed, 22 Jul 2026 03:58:19 GMT

Part Number: BQ41Z90EVM

BQ41Z90EVM

Could you please verify why this IC part number is specified on page 28?

TPS55332-Q1: Portions of no glassivation by design?

Michael Valiente — Tue, 21 Jul 2026 21:11:32 GMT

Part Number: TPS55332-Q1

Hello,

We are performing a destructive physical analysis on TI part number: tps55332qpwprq1.

After performing decapsulation to expose the silicon chip, it was observed that portions of the die do not have a glassivation layer. The metallized portions that do not have a glassivation layer looks like a design choice. I have attached an optical image showing the unglassivated portions (green areas). I also attached a SEM images showing the unglassivated areas (white areas).

Please confirm if these portions of the die are unglassivated by design.

TMS570LS1224: MibSPI1 not working with W25qxx external Flash module

Dnyaneshwar Telange — Thu, 16 Jul 2026 09:57:49 GMT

Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello Team,

I am using the TMS570LS1224 controller-based development kit (LaunchPad XL2).

I am currently trying to interface a W25Qxx external Flash memory module, which communicates over SPI using the following four pins:

MOSI
MISO
CLK
CS

Initially, I followed the steps provided in the HALCoGen examples. However, I found that there is only one SPI example, which uses loopback mode. I tried running that example, but it did not work initially. After enabling the MIBSPI1 interrupt from the VIM tab in HALCoGen, the example started working. This additional step is not mentioned in the provided example.

Using the same code as a reference, I added the logic to read the JEDEC ID of the W25Qxx Flash module. However, the read operation always returns 0xFF.

I have attached a ZIP file containing the HALCoGen project configuration and the sys_main.c file. Could you please review the code and let me know what I might be doing wrong?

Thank you for your support.

mibspi_loopback_demo_w25qxx_not_working.zip

for connections I am using J10 connector and Pins are as follows
1.SCLK ---> J10 - 32
2.MOSI ---> J10 - 35
3.MISO ---> J10 - 33
4.CS0 ---> J10 - 26