Hi Team,
Is there a negative consequence or latch up condition that could occur is voltage is applied to EN/SEL pins before VDD has power?
Thanks,
Jared
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Team,
Is there a negative consequence or latch up condition that could occur is voltage is applied to EN/SEL pins before VDD has power?
Thanks,
Jared
Hi Jared,
No problem applying the EN/SEL voltage prior to VDD being set. This device has fail-safe logic which means the device can ramp its logic pin voltage independently of the supply voltage to help simplify power sequencing.
Let me know if you have any other questions.
Thanks!
Bryan