J721E TDA4 who will cause RXALIGNCODEERRORS？

Hi,

Alignment errors are caused by Pinmux errors where one or more pins are not configured correctly or by Hardware issues. Please check your pinmux and have the schematic reviewed by someone in TI (if not done already)

To get your schematic reviewed, please contact your TI representative.

Regards

Vineet

Hi sir  

Please see our's schematic and the pin setting. Please help check!

static pinmuxPerCfg_t gRgmii5PinCfg[] =
{
/* MyRGMII1 -> RGMII5_RD0 -> T23 */
{
PIN_RGMII5_RD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_RD1 -> R23 */
{
PIN_RGMII5_RD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_RD2 -> U24 */
{
PIN_RGMII5_RD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_RD3 -> U27 */
{
PIN_RGMII5_RD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_RXC -> U25 */
{
PIN_RGMII5_RXC, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_RX_CTL -> U26 */
{
PIN_RGMII5_RX_CTL, PIN_MODE(0) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyRGMII1 -> RGMII5_TD0 -> U28 */
{
PIN_RGMII5_TD0, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
/* MyRGMII1 -> RGMII5_TD1 -> V27 */
{
PIN_RGMII5_TD1, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
/* MyRGMII1 -> RGMII5_TD2 -> V29 */
{
PIN_RGMII5_TD2, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
/* MyRGMII1 -> RGMII5_TD3 -> V28 */
{
PIN_RGMII5_TD3, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
/* MyRGMII1 -> RGMII5_TXC -> U29 */
{
PIN_RGMII5_TXC, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
/* MyRGMII1 -> RGMII5_TX_CTL -> U23 */
{
PIN_RGMII5_TX_CTL, PIN_MODE(0) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
},
{PINMUX_END}
};

Thanks!

Hi,

Pinmux cannot be reviewed like this, it depends on your application use, which other cores are running which application etc.

Please dump the IO PAD registers after complete boot and then compare with expected values.

For schematic review please contact TI representative. I assume that more files would be required to review the layout etc

Regards

Vineet

Hi sir

   Thanks for your reply.

    how to dump the IO PAD registers? we are use QNX+TIRTOS. And our version is ti-processor-sdk-rtos-j721e-evm-07_03_00_07

Hi sir

    Now, the TC397 send ARP to TDA4. The size of the ARP is 78. But the TDA4 shows the size is 83.

          PORT5 STATS

--------------------------------

STAT_5_RXALIGNCODEERRORS         = 109

STAT_5_TXGOODFRAMES              = 1

STAT_5_TXBROADCASTFRAMES         = 1

STAT_5_TXOCTETS                  = 40

STAT_5_OCTETFRAMES64             = 1

STAT_5_OCTETFRAMES65T127         = 109

STAT_5_NETOCTETS                 = 562b

STAT_5_PORTMASK_DROP             = 109

STAT_5_TX_PRI_REG             [1]= 1

STAT_5_TX_PRI_BCNT_REG        [1]= 40

    How to see the detailed data which received from the mac port?