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TS3A5018: PCIE REF CLK Mux/Demux.

Erez Cohen
Prodigy 60 points
Part Number: TS3A5018
Other Parts Discussed in Thread: TS5A2053, HD3SS3411, TS3A5223

Hello,

On my PCIE GEN5 Host design I need to support PCIE_REF_CLK (Connector pins A13/A14) to be an input or output from a SoC. The SoC pin is bidirectional.

The clock should support w/ or w/o SSC.

Could you please advise if the TS3A5018 will work for me?

Thanks in advanced'

Erez.

  • 0
    TI__Mastermind 28048 points

    Hey Erez,

    Could you provide me more information on what lines you are actually muxing? Is it only the ref clk? Is this a standard 100MHz reference? 

    As long as you are at or below the recommended voltages (3.3V) and bandwidth (300Mhz) listed in the datasheet, you should be fine with the TS3A5018. That being said, if you it's only one line that you're muxing, maybe a device with only 1 channel vs 4 channels would be better in terms of space and cost? A 1  channel 2:1 like the TS5A2053 could work

    Thanks,
    Rami

  • 0 in reply to Rami Mooti1
    Prodigy 60 points

    Hello Rami,

    Thanks for your prompt replay!

    I am going to Mux the PCIE REF_CLK_N/P, 100MHz SSC for GEN5 switch. 

    On first place i consider the use of the HD3SS3411. I was said it doesn't supports SSC

    On my application the PCIE slot can populate EndPoint (Blue) or RootComplex (Red)  and REF_CLK signal is input or output respectively. See the below chart.

    My concern is the Jitter. what is the Jitter added by your device if any? Do you have experience with PCIE Gen 5 clock Mux? Should I take other consideration for my application?

  • 0 in reply to Erez Cohen
    TI__Mastermind 28048 points

    Hey Erez,

    Our analog muxes are just passive devices and can be thought of as just an RC circuit. The RC being the on-resistance and on-capacitance. This can be used to approximate device characteristics such as BW, propagation delay, and jitter. The jitter being the change in the propagation delay. Typically this isn't a problem in most switches. The capacitance will stay fairly consistent across use cases, the RON however will vary depending on the RON flatness and for differential signals another interest may be the delta RON (difference of on state resistance between the switches). The less variation in these specs, the less jitter you can expect. So a device like the TS3A5223 would be a good fit to minimize the jitter. 

    That being said, I'm not an expert in PCIE signals so I can't give you any guarantee here. If you could give me more information, I can provide an answer with more confidence. Based on the HD3SS3411 and TS3A5018 choices, it seems that the voltages are =<3.3V. Can you confirm this?
    More importantly, why was it said that the HD3SS3411 wouldn't work for SSC signals? Was there a spec in particular? This isn't one of our devices in the analog switches and multiplexers portfolio but I looked through E2E and found this post that indicates that the device should be fine for SSC clock:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/923410/hd3ss3411-hd3ss3411---ssc-feature-support---reg

    Thanks,
    Rami

  • 0 in reply to Rami Mooti1
    Prodigy 60 points

    Thank you Rami for you detailed answer.

    Regarding the PCIE GEN.5 requirements, please refer the attached spec.

    Regarding the HD3SS3411, this was the answer I got on E2E: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1095092/hd3ss3411-pcie-ref-clk-mux-demux/4055676#4055676

    Can you advise the added Jitter due you recommended solution?

    Thanks,

    Erez

    TI REFCLK GEN5 Req..docx

  • 0 in reply to Erez Cohen
    TI__Mastermind 28048 points

    Hey Erez, 

    Looking at that thread, I don't believe the consensus was that the HDS wouldn't work but rather it was uncertain whether it would work. I'm still not seeing anything that would indicate a problem, but as I mentioned, I don't have much experience here with PCIE or more specifically SSC. Seems to be just a modulated frequency signal; so a carrier signal that is encoded with modulated frequencies. Bottom line, seems to be just an analog signal so it shouldn't be impacted much by these passive devices. 

    So we don't typically spec the jitter since our devices don't really add a lot of jitter. That being said, we can look at the propagation delay to get an idea here of what range we can expect. We have a good FAQ on this : [FAQ] How do I Approximate Propagation Delay and Channel to Channel Skew in an Analog Switch/Multiplexer? 

    The variation in the propagation delay that would effectively be the jitter, which would be impacted by the delta RON. So by looking at the delta RON we can get a rough idea of how that RC will change. So if we look at the TS3A5018 for example, the on-capacitance would stay at 16pF and the Ron max variation is 1ohm. So 1RC time constant there would give us a change (or jitter) of 16ps. Given that this is just an approximation, it still is an order of magnitude greater than the 150ps allowed here. Just keep in mind that the jitter and prop delay will be more heavily dependent on the load itself, outside of the mux. So minimizing the load and keeping trace lengths short would be recommended to help reduce jitter.

    Thanks,
    Rami