SN74CBT16210C: ON resistance when Vin=3.3V or Vin=5V when VCC=5V & usage of multiple ports in parallel

The next-level PCB uses TI's LDO TLV1117LV33 to convert this 5V VDD to 3.3V VCC for internal circuit. This TLV1117LV33 has dropout voltage 455mV with 100us startup time. Thus, this next-level PCB can accept supply voltage down to 3.8V VDD as input to LDO, and still get output at 3.3V for internal circuit.

Can I use CBT, CB3Q, CBTLV to pass 3.3V 20mA to the next-level PCB as the VDD to supply the voltage for this next-level PCB circuit, without using load switch? If yes, it can greatly simplify my design, as there are additional 13 regular 3.3V signals to go together. The next-level PCB can accept the VDD down to 2.8V. This is a different design vs the previous 5V 500mA design.

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Thanks.

Thanks for the reply. As CBTLV can only support 64mA and 3.3V per channel, it cannot meet my 5V 500mA need. The CBT's Ron will go too high based on P-14 of reference you provided, which is impractical to my tolerance of 5V-> 3.8V @500mA requirement.

Thanks for the reply.

Hey Daniel, 

Is there a reason that you're looking to use a signal switch with multiple channels in parallel over something like a load switch? The signal switches typically won't be able to handle as much current so it wouldn't really be an optimized solution as whatever device you end up using won't meet the requirements and you'll need many device to do this, where a load switch can handle the current requirements easier without the need for running the I/O's in parallel.

Thanks,
Rami

There are many next-level PCBs are needed to be scanned and activated one-by-one. There are 13 regular signals to be exchanged, together with 5V (peak 500mA, average 100mA) and 3.3V (peak 20mA) VDD. Thus, I can have plenty of available ports by using a 20/24-bit bus switch. Thus, I am thinking to pass the 3.3/5V VDD together for better timing synchronization. PMOS or load switch to handle VDD might bring in timing a-synchronization issue. That is why I am thinking to use available ports in parallel to reduce the Ron and catch the required current. Should I buy couple 24-bit SN74CB3Q16211 to verify my thought, or just do not waste time as it will not work?

The SN74CB3Q16211 datasheet mentioned ON State Switch Current is +-64mA. Is this the total current allowed from all I/O port, or by each I/O port?

That is per port.

But even using many channels in parallel, you will have a noticeable voltage drop. And deliberately sequencing the power and signal lines might make sense.

Thanks for the reply. The Ron @Vin=5 is 9 ohms for SN74CB3Q16211. When 10 ports are used for 5V (peak 500mA, average 100mA), the max voltage drop across the switch will be around 0.45V (=0.5A *10/9). That is the minimal output voltage will be around 4.5V.

As I used TI's TLV1117LV33 LDO (dropout 0.455V) at the next-level PCB, this great LDO can accept input down to 3.8V in order to deliver stable 3.3 output. I wonder whether it makes sense to verify by experiment.

For the 3.3V (peak 20mA) using only one port, the max voltage drop across the switch will be (0.02A * 5 Ron@Vin=3.3)=0.1V. A 3.2V VDD should be acceptable for the next-level PCB, as our design can accept next-level PCB's VDD down to 2.8V.

However, I am not the expert of this CB3Q switch, do you think it makes sense to buy couple sample to verify? If yes, we will buy some to verify first, and update here later.

Thanks for the reply. Your temperature concern reminds me, We will buy some samples from Mouser to do simple verification before putting to real PCB and will update the result later.