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[FAQ] What are the Types of Architectures TI Switches and Multiplexers Use and how do I know which one my device has internally?


TI switches and multiplexers are often designed using one of three different circuit architectures that enable different characteristics and capabilities depending on which one is selected. The typical architectures can be broken down into three categories: NFET, Transmission Gate, and NFET with Charge Pump. In this FAQ, we will explore the benefits and drawbacks of each architecture and how one can differentiate between them based on common datasheet parametrics and graphs.

NFET Topology:

The figure below shows a simplified FET switch, which consists of an N-channel transistor and gate bias and enable circuitry. The switch is bidirectional; the source and drain are interchangeable (while operating, the side with the lowest VI/O is the source).

For an N-channel FET to operate properly, the gate should be biased more positive than the magnitude of the signals to be passed. This is because the on-state resistance, RON (or RDS(ON) as it also is called), increases as VGS (gate minus source voltage) decreases. If the VI/O signal approaches the magnitude of VCC, VGS decreases and RON increases (see below example with device VCC at 5V). The ability to maintain a low RON in a FET switch depends on maintaining VGS as large as possible:

An N-channel FET can be used to implement a level translator. This switch can pass a signal from 0 V to VCC – VT, where VT is the threshold voltage of the NMOS. This characteristic can be used for down translation. For voltage-translation applications, the switch is required to translate efficiently over a wide frequency range and is required to maintain the proper signal level. For example, when translating from a 5-V TTL to a 3.3-V LVTTL signal, the switch is required to maintain the required VOH (output high voltage) and VOL (output low voltage) of 3.3-V LVTTL signal. One important consideration is that the switch can be used only for down translation, for example, high to low level. For low- to high-level translation, additional components (for example, pullup resistors) are required.



Simple Implementation

RON increases when VGS is lowered

Can be used to incorporate voltage translation

Switch may turn off if VGS drops below VT

How to Determine from Datasheet

Incorporate voltage translation

RON curve is often missing

If RON curve is present, only a few points are present on the graph

Transmission Gate Topology:

The Transmission Gate topology is the most common architecture that switches will be built on and will often consist of a single N-channel transistor in parallel with a single P-channel transistor (see below). These are also known as Transmission Gate switches:

As before, when VI/O approaches VCC, the N-channel conductance decreases (RON increases) while the P-channel gate-source voltage is maximum and its RON is minimal. The resulting parallel resistance combination is much flatter than individual channel resistances (as shown below).

A flat RON is especially important if VI/O signals must swing from rail to rail. However, the tradeoff is increased switch capacitance due to the additional P-channel transistor and associated bias circuitry.



Passes rail to rail voltages

Increased internal capacitance

Lower RON than single NFET


Improved RON flatness


How to Determine from Datasheet

RON curve given in the datasheet

RON curve has multiple “humps” and is relatively flat


NFET with Charge Pump Topology:

TI also offers N-channel signal switches with charge-pump-enabled pass transistors. A design of this type (as shown below) allows the gate voltage to be higher than VCC.

This increases VGS above what is possible in noncharge-pump devices and allows signals at or above VCC to be passed. A switch of this type has the advantage of low, relatively flat RON (over the signal range), without the addition of a P channel and while maintaining internal capacitance values comparable to pure N-channel FET switches. This performance comes at the expense of increased ICC (from a few µA to several mA in some cases). Below is an example of the typical RON curve for devices with an NFET with Charge Pump architecture:



Lower RON and CON

Increased power consumption

Smaller Solution Size


Above the rail operation


How to Determine from Datasheet

Device can pass signals above the supply rail

RON curve similar to single NFET, but does not exhibit large RON performance