This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AUC2G66: Reference/Example schematic

Part Number: SN74AUC2G66
Other Parts Discussed in Thread: SN74LVC1G66

Hi Team,

Do we have any EVM or reference design that includes SN74AUC2G66? My customer is looking for an example schematic or application note so that they can refer to it while they drawing their schematic. I cannot find any relevant document in product folder. Just FYI, they're using SN74AVUC2G66 for zero delay buffer for 25MHz AVBus. Thanks.

  • See sections 9 and 10 of the SN74LVC1G66 datasheet.

  • Hey Ella,

    Could you maybe expand on the use here? Are they trying to use the SN74AUC2G66 as a zero delay buffer or are they using is as part of their implementation for creating a zero delay buffer? Just want to be clear that this is a passive device and won't buffer any signals.
    The application section of the SN74LVC1G66 datasheet will work here. The only recommendation would be to stick to the datasheet limits and a decoupling cap on the power supply. A 0.1uF should suffice as close to the device as possible.


  • Hi Rami,

    Just want to be clear that this is a passive device and won't buffer any signals.

    May I ask for more elaboration on this comment? What exactly mean by "passive device" and "buffer any signals"? Is it something to do maybe with input impedance or output driving capability? 

    They're going to use SN74AUC2G66 as a zero delay buffer. They need to use it between Master SoC and slaves for AVSBus series interface. I was looking for a min delay buffer from INT-LOGIC product line but I notice SN74AUC2G66 has the shorter Tpd delay than other INT-LOGIC devices and select SN74AUC2G66 for suggestion.

  • Ella,

    Passive device just means that it's an analog switch that can basically be modeled as a resistor with some capacitance. This FAQ shows a good example of that [FAQ] How do I Approximate Propagation Delay and Channel to Channel Skew in an Analog Switch/Multiplexer?
    So you are correct about the output driving capability. A analog (passive) mux will not have any output drive while a digital mux (what you find the in logic portfolio) will.
    Both devices will have pretty low propagation delays but both will be pretty dependent on the load since both are pretty simply CMOS architectures. As you saw though the passive devices tend to be a little lower. 

    My understanding of a zero delay buffer is that they need to have buffered clock inputs that is fed to multiple sources but requires a PLL to stabilize the clocks. Using just a SPST mux like they're looking to use now will only be able to connect/disconnect the clock, which isn't quite the same. Which is why I ask if this is being used as a zero delay buffer or part of a circuit to support a zero delay buffer implementation. Do you by chance have a block diagram of what they're aiming to do?


  • Hi Rami,

    Thank you a lot for comment! While I'm under discussion with customer, please let me double check. 

    (1) I think the block diagram maybe mislead them to think SN74AUC2G66 as a bidirectional buffer. The diagram looks like a buffer which has output driving capability. I'm wondering if it's a generic diagram for this passive SPST.

    (2) Below is simplified diagram for SPST switch. Can you help confirm if this structure is also applicable to SN74AUC2G66?

    (3) These questions are regarding the working theory of SN74AUC2G66.


    While C = 1 --> Channel ON,

    when A is driver : B is HIGH --> A falls to LOW --> Driver at A side sinks current from B side (thru n-ch FET) --> B falls to LOW

    when A is driver : B is LOW --> A rises to HIGH --> Driver at A side sources current into B side (thru p-ch FET) --> B rises to HIGH

    when B is driver :  A is HIGH --> B falls to LOW --> Driver at B side sinks current from A side (thru p-ch FET) --> A falls to LOW

    when B is driver : A is LOW --> B rises to HIGH --> Driver at B side sources current into A side (thru n-ch FET) --> A rises to HIGH


    Can they mix the pull-up and pull-down for A/B pin? We can suppose that A side is pulled up to 1.8V thru 4.7kohm while B side is pulled down to GND thru 4.7kohm. When drivers on A and B side are both in HI-Z status, A/B pin would show 0.9V (1.8V/2) by resistor dividing (Rdson is ignored). Is my understanding correct?



  • Hey Ella,

    1-2 : 
    I definitely see how this can be confusing. You are correct here, the second image (transmission gate architecture) is a good simplified diagram to use. 

    Your assumptions are right here. You are shorting the A and B side. What will actually be seen though will technically depend on the impedance of the driver and any pullup/downs resistors. That being said, in your example you are correct. You can put a pull up on one side and a pulldown on another and create a voltage divider. Of course, as you mention, Rds(on) is ignored so you wouldn't be quite at 0.9V.


  • Hi Rami,

    Thank you for your help here. 

    I've checked customer's requirement : they need a "switch", not a "buffer".  They need to cut off the AVSBus line during a specific period of operation. Their selection of word "zero delay buffer" earlier caused a confusion. They will go for SN74AUC2G66.