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SN74CB3T3245: level translation 5v to 3.3v MII bus

Part Number: SN74CB3T3245
Other Parts Discussed in Thread: SN74LVC541A, TXV0108,

Tool/software:

I am looking to implement a single fixed direction logic 8bits wide logic solution from 5V domain to 3.3V to Domain. Actually a MII RX only interface from older 5V DSP PHY chip to 3.3 FPGA.

So this needs to run at 125Mb/s but i am aiming for something >200Mbs to give some design headroom.

Since this is down convert only and drive capability is not a an issue i initially selected the CB3T part. Now I am reviewing the design, I am wondering if this device will be fast enough, some data i have seen suggest <100M.

I have been wondering if another simpler 5v tolerant family with actiive drivers, such as AVC, might be faster/ better ?

It further occurs to me that some active logic parts have built in series terms on their outputs. This would avoid the need for the descrete external 33ohm resistors i have at the output of my 5v DSP PHY.

Thanks for any help

Chris

  • The fastest logic family that tolerates 5 V is LVC. At 3.3 V, the SN74LVC541A would support about 175 MHz. (Faster devices like the TXV0108 do not support 5 V.)

  • Hey Chris,

    Are all 8 bits data bits? And is the 125Mb/s total transmission or across those 8 bits (so really about 15MB/s per data line)?

    Whatever the configuration is, you'll likely need about 5x the signal frequency as your mux bandwidth, since these are likely square waves you you'll want to capture the higher frequency harmonics to maintain the sharp edges.

    So if all 8 bits are data and you really need 15.625MB/lane you should be fine with the SN74CB3T3245 device. I'd pick something with a bandwidth about 78MHz which the 3245 will have.
    If we need higher, I may need to loop in someone from our Logic team for a higher frequency performing translator device. 

    Thanks
    Rami

  • good point on the data lines (there are actually 4) so indeed a quarter of the rate but i am currently putting the clock thru the same buffer and some other signals too, to keep skew the same. So do need higher just to handle the clock line. thanks

  • Would the clock also be 1/4th the data rate then? I'm assuming here this is only being read on a single edge so with 4 data lines you'll probably be good with a 31.25MHz clock reading 4 samples per cycle (=125MB/s).

    If that's the case, you'd be pushing the limits of the 3245. You'd probably be fine with good routing and minimizing the trace lengths but ideally you'd have something that can support a little bit higher frequency. It would be a bit load dependent as well but I'm assuming high impedance load here. 

    I hadn't seen Clemens suggestion above, I think we pressed reply at the same time. But his suggestion on SN74LVC541A and utilizing the overtolerant inputs. Looping in our logic team for confirmation

    Logic team, any concerns on the SN74LVC541A being used as a voltage translator from 5V to 3.3V at higher frequencies (maybe up to 31.25MHz but still confirming)

    Thanks,
    Rami

  • just to confirm clock rate is 25mhz, 100 not 125 overall bw, apologies.

  • Hi Chris,

    Yes the SN74LVC541A should be able to down translate from 5V to 3.3V at 25MHz just fine.

    Best,

    Malcolm

  • thanks for all the help

    Best Regards

    Chris