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TS3A5223: I2C READ FAIL

Jooeun Kim
Prodigy 10 points

We're currently communicating with SMBUS and I2C via a MUX. Due to an I2C READ communication failure occurring through the MUX, we checked the MUX output and found that PIN 3 (CON1) SCL was not dropping low but was maintaining 2.9V. This appears to be the reason for the communication failure after 10 RETRY attempts.
The input PIN 2 (NO1) is dropping low (0V), and both the MUX's appearance and X-ray images confirmed no problems.
We checked the pin impedance of the MUX and found that PIN 8 (IN2) was 7.7 ohms. The PIN 1 (VDD) impedance was also 426 ohms.

However, when removing the MUX, the PIN 9 and PIN 10 pads fell off. This raises questions about the feasibility of the product's FA.

  • 0
    TI__Expert 3435 points

    Hi Jooeun,

    Could you please provide details about your I2C read failure?

    Thanks!
    Katy

  • 0 in reply to Katy West
    Prodigy 10 points

    I apologize. I wrote something in the post, but I deleted it because I thought it was in the wrong location. I've edited it, so please check. Thank you.Joy

  • 0 in reply to Jooeun Kim
    TI__Expert 3435 points

    Hi Jooeun,

    No worries - thanks for updating. Are you able to probe the source of the SCL line and compare it to pin 3 on the mux? The mux is a passive mux, so should just be passing through the signal it sees. If you are seeing something abnormal, it's likely due to the source of that signal.

    If you need further help, I'd be happy to review your schematic.

    Best,
    Katy

  • 0 in reply to Katy West
    Prodigy 10 points

    7585.TS3A5223RSWR_FA.pptx

    Thank you for your reply.

    Yes, I've already compared them. I've provided a more detailed explanation in the PPT.

    I checked the SCL input pin (PIN2) and the output pin (PIN3). PIN2 drops to 0V, but PIN3 only drops to 2.9V.
    If possible, please check the PPT.

    MUX is currently included in the company's SSDs, and the SSDs have undergone the following tests at customer sites:

    They confirmed that the SSD sample had undergone FIO tests, Oakgate IO tests, and MI-related tests prior to the failure.
    They didn’t perform any ESD testing on the failed sample before.

    Is it possible that these tests resulted in damage to the MUX?

  • 0 in reply to Jooeun Kim
    TI__Expert 3435 points

    Hi Jooeun,

    You could please provide the schematic, voltage levels on each pins, and state of the mux (ie open/closed)? Could you also please elaborate on what voltages/currents/etc are used during the SSD tests? This will help me continue to debug.

    Best,
    Katy

  • 0 in reply to Katy West
    Prodigy 10 points

    Hi, Katy.

    I've attached the MUX-related circuit diagram.
    Please check it.

    Best,

    Jooeun

  • 0 in reply to Jooeun Kim
    TI__Expert 3435 points

    Hi Jooeun,

    No concerns from my end on the schematic. Not sure the details on the SSD tests, but depending on voltages, that might be the culprit.

    Best,
    Katy

  • 0 in reply to Katy West
    Prodigy 10 points

    Hi Katy,

    I'm sorry, but I don't think my question was properly communicated.
    The issue I'm facing has been resolved to a single MUX defect.
    I'd like to ask if your company can perform a FA on the defective MUX I have.
    However, the instructions state that all pins on the MUX must be intact when FA is performed. However, during rework, PINs 9 and 10 were removed.
    I'm inquiring whether a failure analysis can be requested in this condition.

    (Is this the right place to ask this question?Fearful)

    Thank you.

    Jooeun

  • 0 in reply to Jooeun Kim
    TI__Expert 3435 points

    Hi Jooeun,

    Thanks for clarifying! You can go to the product returns page and then a regional quality engineer will reach out to you to discuss whether the unit can be returned or not.

    Product returns | myTI | Texas Instruments

    Best,
    Katy