Hello,
We have an issue with the TS5A3159AYZPR where it is basically used as a tri-state buffer. Normally Open (NO) is tied to a CPLD signal this is used a Chip Select for a battery backed SRAM. NC is left floating, and IN is tied to a voltage level detect circuit that monitors if main power is present, or if the system should switch to the backup battery. V+ is tied to a 3.3V rail produced by main power. The thought was that as main power is lost, IN would go low, switching NC to COM, turning it into a high-Z line. The CS_N (COM) is pulled high through a 10k to Vbackup battery (3V).
Instead, the COM seems to follow V+ and NO slowly down until power is almost completely gone. This is causing the CS_N to fall briefly and corrupting the first byte of the memory. We've tried holding IN low while V+ is still fully powered, and then removing power. COM falls a little faster, but still isn't high impedence until V+ is really low.
Is there something internal to the part that would prevent an open NC pin from looking like a high-Z line when connected to COM? or anything else that could explain this performance?
Thanks,
Eric
