Hello,
My customer is planning on using the TSU6721 and they have some concerns on the timing of the detection mechanism for BC1.2 that this switch includes, and how it will play with the detection in their existing platform. Please see questions below:
The datasheet is a little light on details, so I’m hoping you can help to answer a few questions I have:
- Looking for any description of the timing / sequence of events when the part is in “detection” mode. I understand it waits for VBUS, then begins a detection routine including the ID pin and the D+/D- impedances. Just need to understand how long this process takes after VBUS is valid.
- During detection mode, what electrical state is the switch in? I’m assuming it’s fully open (meaning Hi-Z looking into the USB terminal from the SoC).
- After detection is done, how long does it take to switch over to the USB path in automatic mode? Is this done in parallel with the VBUS load switch, or serially?
- This is getting at the issue that our BC1.2 detection begins when VBUS is valid (at our PMIC, meaning out of the TUSB switch). Ideally I would find out that by the time the VBUS switch gets fully thrown by the TUSB switch, the data lines are already switched over to the USB analog path.