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What is state of the I/O channels when the CD4051B is at the beginning of power-up?

Fabio Bucci
Intellectual 2615 points
Other Parts Discussed in Thread: CD4051B, SN74CB3Q3251, SN74CBTLV3251

Team,

What is state of the I/O channels when the CD4051B is configured as a demultiplexer at the beginning of  power-up (rising edge of voltage supply)?

Pins A,B,C are shorten to ground potential, INH pin is usually shorten to the ground, but if it is really necessary it could be connected to the supply voltage (already rising actually). 

The same story is for falling edge of supply voltage. 

The most important for me is to avoid situation where state is not exact defined.

  • 0
    TI__Mastermind 45475 points
    Bo345,

    I took quick look at the datasheet and didn't see that there is a defined state at power up. Most of our switches do not have default logic settings so we usually recommend our customers place some sort of pull up or pull down on the digital control pins to define a state on power up.

    We do have some switches that have a powered off isolation feature which places the signal paths in high impedance when the supply to the IC is 0 V like the SN74CB3Q3251. This type of device would have a defined state on power up with the signal paths being in high impedance until the digital control is selected to conduct.

    I have contacted the engineer supporting the CD4051B for more information on the device.

    Thank you,
    Adam
  • 0 in reply to Adam Torma
    TI__Intellectual 2615 points

    Hi Adam,

    many thanks for your prompt reply.

    Please keep me posted on the feedback you get from the engineer supporting the CD4051B.

    Thanks

  • 0 in reply to Fabio Bucci
    TI__Guru 59050 points
    Bo345 ,

    As Adam mentioned in the post , it is undefined / indeterminate. With INH high or tied to Vcc , the channels are in Hi-Z, that however happens after the Vcc reaches a certain threshold w.r.t INH.
    Devices with power-up-3-state will ensure that the channels are in Hi-Z with Vcc ramping up/down to reach a certain point after which the INH tied to Vcc will ensure the high impedance. This refers to level 2 isolation with Ioff as Level 1 isolation.
    I could suggest other devices based on your requirements but sn74CBTLV3251/ Sn74CB3Q3251 is a start in the right direction which have Ioff.
    another note, please ensure there are no active I/Os when Vcc is 0 and ramping up. This may damage the device with excess current.