Hello!
I've got a prototype design using an SN74CBTLV3384 bus switch, used to protect the input pins of a modem IC.
The modem does not have a traditional RESET input, and reset is only possible by cutting it's power source. During that, the pins of the modem should be protected. The modem communicates at 2V8, and the manufacturer recommends using level shifters with high impedance mode to connect the IC to a 3V3 system, and protect it's pins during these "resets". To reduce the possibility of error and remove the need to use level shifting, I designed the whole system to use 2V8, and added the above switch to protect the input pins of the modem when it is not powered (not only during reset, but to reduce power consumption too, when the modem is not needed). So, the VCC, the control signals, and the signals routed by the switch are all 2V8.
Anyways, I've got SPI, UART, IIC and some GPIO pins routed through the bus switch, all running perfectly fine, even at high speeds (UART at 460800 baud, SPI at 10MHz), except for the IIC (40kHz). I regularly get errors, about 50ppm transfers are ruined. Of course, nor the modem, nor the MCU on the other end of the channel use the exact IIC protocol, so the problems could be caused by software, or peripheral errors. After looking at some oscilloscope measurements the manufacturer of the modem suggested that the switch may cause the problem. (Sometimes strange voltage levels appear on the line at about 1.4V, but my bet is on the modem using push-pull to control the IIC line, instead of open-drain.)
So, my question is :
- Is the above design to protect the pins of the modem viable?
- Can the switch somehow cause errors, like pulling the line low when using IIC?
- If so, can you suggest some more robust design? (The cost of the solution is very important.)
Thanks for your help in advance!