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TS3A5017: Selected channel during transition of input select signals

Takashi Onawa
Genius 13200 points
Part Number: TS3A5017

Hi Team,

I would like to know TS3A5017's behavior at input select signal transition timing. I understand the Input select signals should be ideally reached to the pins at same time but there should be some skew between the signals in fact. Due to the skew, I think undesirable logic condition is developed untill transitions are completed.

Could you tell me what is happened in the condition?　
Is there a possibility that it will be connected to an undesirable channel?

Regards,

Takashi Onawa

  • 0
    TI__Mastermind 45400 points

    Takashi-san,

    You can see the behavior of the signal path with respect to the digital logic select pins with the ton and toff specs.  You can see that the FET turning off will happen a little faster than the other FET turning on but we cannot guarantee that one will be completely Hi-Z before the other is low impedance for the TS3A5017 . 

    However we do have devices that have a feature called break before make which means there one FET will be completely off for some specified time before the other FET turns on.  You can find a device like this on our parametric search tool.

    What are you doing with the switch that you need to make sure one channel is off before the other one is on?

    Thank you,

    Adam