SN74CBTD3861: Voltage translation with and without FPGA logic loaded

Hello BMA,

When the FPGA logic is implemented, there is generally a front end GPIO where current can be sunk/sourced allowing the designated values of 1 or 0 to be passed onto the upcoming registers. However, when your FPGA does not have logic, that portion of the FPGA is not active, therefore not current is sunk or sourced. Since you have a pull up resistor to 5V on the DSP end and there is no current being sunk or sourced, there is no voltage drop across the switch, so it stays at 5V.

These current sinking/sourcing specs can be determined by the termination standards supported by your FPGA, but they are only chosen when you have logic loaded on the FPGA since most FPGA's support multiple (LVDS, LVCMOS, etc.)

Thank you,

Louie

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Hello,

Please see the post I made regarding these kinds of scenarios:

There are a few things that I would like to ask and clarify before proceeding further.

This is what I imagine your circuit to be currently:

If that is correct, then could you please provide the speed which you are pulsing the signal, marked in blue? Also what voltage does your customer see at that node? 

To address the first point your customer mentioned about the node under the high lighted resistor, this instance can be caused by a series of things. One of which being the power up sequence which the 3V3 turns on. If the 3V3 turns on later than the 5V signal gets there, then the same phenomenon I mentioned in the previous post will still happen. Could you please check that is not the case.

To the second question posted:

Although you are correct that a NMOS switch's voltage is controlled by the gate, it is also dependent if there is a path for the current to go. So in the original instance, your switch went to a floating point when the FPGA wasn't programmed. In this new instance, you now have a path for current to flow through 3V3, but as mentioned, a series of factors can play into effect about whether it starts at 3V3 or 5V0.

As for the note about Vt is a characteristic of the switch, it is not dependent on the current consumption of the switch:

en.wikipedia.org/.../Threshold_voltage

The voltage set at the gate of the switch is dropped so that you will have a higher impedance than most switches which is what allows the translation from 5V to 3V3.

On a final note, it appears that a 5V to 3V3 isolation is very important in your application regardless of the FPGA logic state, I would like to suggest/pass this to our voltage translators forums as they may be able to off you a solution with more isolation than our switch. Attempting to perform this kind of isolation with a pull up could hurt your system as well as the switch, if you want to do an application like this, we would recommend reducing the strength of the pull up to 3V3, because you are pulling a certain amount of current with two 1 kOhm resistors. 

Regards,

Louie

Hello,

These are very interesting scope shots. Thank you so much for grabbing these, they are actually quite enlightening.

With that being said, there are some things to observe from these:

If we look at the scenario you have presented in scenario 1 and 3, they contradict on another. How did you set up scenario 3? This scenario contradicts scenario 1 because if you it starts off at 3V3. My question would be, how did you set that output value to 3V3, or had you waited some time for it to settle to that value?

Scenario 1 affirms what we had spoken about in the previous post. But if you look very closely at the second part of scenario 1 with a pull up resistor and scenario 2 that you posted (programmed FPGA), you will note that they are actually similar in behavior, just not settling time. In scenario 1, with a pull up resistor on the FPGA side, it settles very slowly to 3V3, where as in scenario 2, it settle quite quickly to 3V3. So in a sense, the pull up you place in scenario 1, is a mimic of what will happen when the FPGA is programmed.

Now to discuss scenario 3, I was looking at the pulses of your scope traces, and the first thing I notice is that they are quite fast. However, scenario3 is the same as scenario 1(without the pull up resistor on the FPGA side), with the exception that it starts off with the output and the input are at the desired voltage levels. How did you get the voltage levels to the desired values, was it by means of:

1) pull up resistor to 3V3?

2) Programmed FPGA to get it to 3V3, then unprogramming it?

3) No pull up, no programmed FPGA, and just turned on switch and waited until it reached 3V3? If it was this case, could you provide a scope trace of this?

I have also noticed that in all of the scope traces you provided, the pulses and the time range on the oscilloscope are not consistent throughout your measurement process. It helps to keep them the same so that we know we are comparing apples to apples. 

Thanks,

Louie

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