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TS5A23159: JTAG clock signal in 2V

Part Number: TS5A23159

Hi Sir,

My customer design TS5A23159 as a JTAG switch as below.

The COM1 connect to CPLD JTAG CLK and NO1 connect to CPU JATG CLK.

And capture the waveform as below. We found the NO1 will have knee when voltage up to 2V as CH3(green) when working well.

Also found the COM1 waveform had claimed in 1.9V when the clock doesn't work.

Did you see this kind of phenomenon before? and any comments on it?

Please help on it, thank you.

  • Hi Anne,

    Thank you for posting here on e2e. 
    I couldn't see any mistakes on in the schematics. Can you find out with what the JTAG_CPLD_TCK is driving? (voltage, current, passives?)
    We'll also need the load that it is driving.

    An easy way to simulate the switch is to replace it with a 2 Ohm resistor and simulate/test if the source supplies enough power. 

    Best regards,

    Ambroise