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SN74LVC1G66: SN74LVC1G66 use on SPI CLK design will encounter distortion.

George Liu1
Intellectual 1570 points
Part Number: SN74LVC1G66
Other Parts Discussed in Thread: SN74AUC1G126, SN74LVC1G126

Hi Sir,

Our customer encountered the problem that the used SN74LVC1G66 on SPI CLK switch, but they meet the CLK will getting distortion.

Could you please help to check if SN74LVC1G66 suitable for SPI CLK? And any other suggestion parts for SPI CLK? (1:1 SPST with SPI support)

Please refer to the picture below, the CLK is around 33MHz.

Thanks,

George

  • 0
    Guru 243820 points

    Were these waveform really measured with a 50 Ω probe? SPI signals require a high-impedance load.

    These look like signal reflections. How long are both traces?

    For a unidirectional signal, you could use a simple buffer like the SN74LVC1G126 (or SN74AUC1G126 if the voltage is not above 2.5 V).

  • 0 in reply to Clemens Ladisch
    TI__Genius 9132 points

    Hi George,

    For digital applications we recommended the switch bandwidth be 1.5 times the datarate per lane or 3 time the clock frequency per lane.

    For SPI CLK at 33MHz, the 300MHz bandwidth of SN74LVC1G66 should work for your application. Most SPI applications require 4 channels, how are you using a 1ch 1:1 switch in SPI application?

    One quick way to if the switch is causing issues or if it is a system issue is to remove the device and short the pins together on the board. This will allow you to run tests with the device removed but the system still configured to pass through your signals. Try this to see if signal distortion is still an issue.

    Can you provide more information on VDD, input voltages?

    Here is a good application note on High speed layout guidelines. Common techniques to reduce clock distortion are to have proper termination where the source impedance matches the termination impedance,  reducing the slew rate of the clock signal, reducing the trace length.

    Regards

    Saminah