We are using SN74CB3Q3257 as aSPI Mux. The B side connected to BMC and CPLD and A side connected to Flash,.
Pin-14 (4B1) and Pin-13 (4B2) are shorted together and used for CS# driven by CPLD (Max10)
We see the logic low is offset to 1.43V (when CPLD Io is LVTTL and 8mA)
The logic low is 1V when CPLD IO is LVCMOS 2mA.
The other signal like CLK, MISO, MOSI driven by CPLD looks okay.
Is there any internal circuit issue with SN74CB3Q3257 which may not allow shorting to pins ???