Switches & multiplexers forum - Recent Threads

TMUX7612: TMUX7612 – Maximum Continuous Switch Current with Multiple Channels ON Simultaneously

Gilbert Cabarles — Tue, 03 Nov 2026 13:45:02 GMT

Part Number: TMUX7612

Hello TI Support Team,

I am evaluating the TMUX7612 for a high-current analog switching application in our PMU (Parametric Measurement Unit).

According to the datasheet, the TMUX7612 specifies a maximum continuous switch current (IDC) of 470 mA at an ambient temperature of 25°C.

I would like to clarify how this current rating should be interpreted when multiple internal switches are operating simultaneously.

My questions are:

Is the 470 mA continuous switch current rating specified per individual switch/channel, assuming only one of the four internal switches is ON?
If all four switches are ON simultaneously, can each switch independently carry 400 mA continuously, meaning a total current of 1.6 A distributed across the four channels?
If the 470 mA rating is applicable per channel, are there any additional restrictions on the total package power dissipation or maximum allowable current when multiple channels are conducting simultaneously?
Does TI provide a derating guideline, thermal calculation, or recommended maximum continuous current per channel when two, three, or all four switches are ON simultaneously?

Application details:

I am considering using the TMUX7612 in a PMU switching matrix with the following configurations:

500 mA current range: Two switches connected in parallel, carrying approximately 250 mA per switch.
1.2 A current range: Four switches connected in parallel, carrying approximately 300 mA per switch.

The objective is to determine whether the TMUX7612 can reliably support these configurations under continuous-current operation, while maintaining the device within its specified electrical and thermal operating limits.

I would appreciate your clarification on the current rating interpretation and any thermal considerations for simultaneous operation of multiple channels.

Thank you for your support.

RE: TMUX7612: TMUX7612 – Maximum Continuous Switch Current with Multiple Channels ON Simultaneously

Nir Gilgur — Tue, 03 Nov 2026 20:24:04 GMT

Hello Gilbert,

1. The 470mA specification is per switch. You can have all channels enabled with each one carrying 470mA of current at the same time for a total of 1.88A.
2. Yes.
3. No, this rating is for all channels passing this current without any additional restrictions. Though, note the device will get hotter and performance will be affected according to that (Ron and current leakage).
4. The 470mA spec is for all four channels enabled at the same time. We also have a thermal calculation guide here.

The TMUX7612 can support your application since not a single channel is passing current higher than 470mA.

Thanks,

Nir

RE: HD3SS3220: HD3SS3220IRNHR Not working

Nir Gilgur — Tue, 03 Nov 2026 19:33:43 GMT

Hello Jay,

It sems like the schematic was posted in way where if I zoom in it becomes very blurry, but I do have a couple of comments.

I don't see a 200k pull up resistor on the DIR pin. Can you confirm it is implemented?
The AC coupling is not implemented correctly. I recommend removing the capacitors on the RX pins, they are not needed.
A good rule of thumb is to AC couple the TX or RX lane, not both.

Can you share a PDF version of the schematic?

Thanks,

Nir

HD3SS3220: HD3SS3220IRNHR Not working

jay Carlo — Tue, 03 Nov 2026 09:55:15 GMT

Part Number: HD3SS3220

Hello,

I have design our custom board using ULPI USB3320 and USB3.1 superspeed TUSB1002RGER and DRP HD3SS3220IRNHR.

USB2.0 is working as intended when VBUS is always ON (HW Strap), however, I cannot enumerate USB3.1 when VBUS is controlled by HD3SS3220IRNHR.

CC1/CC2 when there is no USB device its 13HZ waiting for device. Once USB Device is plug in CC1 or CC2 is 0.3V. And DIR is High in one direction (0deg) and Low on 180deg USB plug in.

There is no Fault as well its high. Voltage 5V and 3.3V are within range.

VBUS is normal when a device is plug in VBUS switch is turn ON.

TXp/TXn is toggling 170Hz when no USB device is plug in.

Not sure why USB3.1 superspeed is not enumerated.

Attach is the schematic.

SN74CB3Q3345: VQFN package information

Jeff YANG — Tue, 03 Nov 2026 07:42:08 GMT

Part Number: SN74CB3Q3345

Hi team,

Does there have SN74CB3Q3345 VQFN package information?

I can't find it in datasheet. thanks!

Jeff

RE: SN74CB3Q3345: VQFN package information

Nir Gilgur — Tue, 03 Nov 2026 19:24:20 GMT

Hello Jeff,

See package details below.
e2e.ti.com/.../4225320.pdf

Thanks,

Nir

TMUX7462F: TMUX7462F: drain pin absolute maximum (VFP + 0.7 V) vs. drain levels blocked when powered off

Jiahui Gao — Tue, 03 Nov 2026 02:06:06 GMT

Part Number: TMUX7462F

Hi team,

We are designing a channel protector stage with the TMUX7462F (TMUX7462FPWR, datasheet SCDS394B) in front of a TI ADS131M08 ADC in a power quality meter, and we have questions about the drain pin rating when the part is unpowered or partly powered.

Our supply arrangement:
- VDD = VFP = +5 V through a TPS22918 load switch with quick output discharge, turned off by a TPS3840 supervisor on the ADC supply.
- VSS = VFN = about -3.3 V from a TPS60403 inverter. On one side the inverter is fed by its own TPS7A2033 LDO from +5 V (behind a BAT54 input blocker), so VSS also collapses after +5 V is lost, at the rate its capacitors set. On the other side the inverter shares the ADC's +3.3 V analog supply, so VSS can stay up after VDD is gone.
- DR tied to VDD (drain Hi-Z on a fault). GND connected.
- Source: behind external clamp strings with 4.99 kOhm in series; the clamped node stays within about +/-1.5 V in normal use and under faults.
- Drain: 2.49 kOhm in series to the ADS131M08 input, 1.2 nF (voltage channels) or 220 pF (current channels) to ground at the ADC pin, and a 100 kOhm bleed to ground. No active source on the drain side. ADC input absolute maximum AGND - 1.6 V to AVDD + 0.3 V, pin current +/-10 mA.

With VDD removed and VSS still present, the part sits at VDD = 0 V, VSS = -3.3 V, VDD - VSS = 3.3 V, below the UVLO minimum of 5.0 V (falling), so it is "powered-off" by the definition on page 25.

The statements we cannot reconcile:
- Absolute maximum ratings, page 4: VD, drain pin (Dx) voltage, VFN - 0.7 V min, VFP + 0.7 V max. With VFP = 0 V that is +0.7 V max on the drain.
- Section 8.3.2.2, page 26: "Source and drain voltage levels of up to +/-60 V are blocked in the powered-off condition."
- Page 28: "The voltage on the drain is only allowed to swing between VFP and VFN and no overvoltage protection is available on the drain side."

The case that matters to us: an input fault (+12 V or +60 V behind the clamp) is present while +5 V is lost quickly (a hard short or a 20 us drop). The ADC supply stays up, so the source node sits at about +1.4 V, the channel stays on until VDD - VSS falls through UVLO, and the drain node and its capacitor are left at about +1.3 V while VFP has already fallen toward 0 V. A simulation of an earlier revision showed the drain up to about 0.6 V past VFP + 0.7 V for under 20 us, with drain current in the microamp range, while the bleed and the ADC input discharge it. That is a model result, not a measurement.

Questions:
1. In the powered-off condition (VDD = 0 V, VSS = -3.3 V, GND present), which rating applies to the drain pins: the page 4 absolute maximum (VFP + 0.7 V) or the page 26 statement that drain levels up to +/-60 V are blocked? Is the page 26 statement meant for the source pins only?
2. If the page 4 limit applies: what is the failure mechanism on the drain side when VD exceeds VFP + 0.7 V (we assume an ESD diode from Dx to VFP/VDD), and is a short excursion (about +1.3 V on Dx, under 20 us, current limited by the external network to well under 1 mA) acceptable, or must the drain be held within VFP + 0.7 V at all times?
3. Between the UVLO threshold (5.0 to 6.4 V) and the 8 V minimum VDD - VSS in the recommended operating conditions: is the switch guaranteed off, guaranteed on, or undefined? We cross this window on every power-up and power-down.
4. The leakage tables are specified at VS = +/-60 V. Is there any data for source and drain leakage with the supplies removed (or VDD = 0 V and VSS = -3.3 V) and a source voltage of only about +/-1.5 V?

Please also answer for each of these cases, for a +/-60 V level on a source pin and for a +/-1.5 V level (the clamped node), giving the guaranteed drain voltage or leakage and the rating that applies:
5. All four supply pins (VDD, VSS, VFP, VFN) at 0 V and grounded; GND present; with DR grounded and with DR tied to VDD.
6. All four supply pins floating (unpowered, no path to ground); GND present.
7. Mixed: VDD = VFP = 0 V grounded with VSS = VFN still at -3.3 V; and the reverse, VSS = VFN = 0 V with VDD = VFP = +5 V (the inverter lost first).
8. Transitions: power-up with the fault already present at the source (VDD rising through UVLO while VDD - VSS is below the 8 V operating minimum), and power-down with the fault present (VDD falling through UVLO, then VSS collapsing).
9. For each case, whether a drain-side pull to a still-powered ADC rail (through 2.49 kOhm, 100 kOhm bleed, 220 pF) violates any rating, and the maximum drain leakage into that node.

10. A related question on the TPS60403 that supplies VSS/VFN: what is its maximum output resistance (or minimum output voltage at a stated load) with VIN = 3.3 V over -40 to 85 C? The datasheet's 15 Ohm maximum is at VIN = 5 V, 25 C only. Our budget needs VSS at or below -3.000 V at the TMUX pins so VDD - VSS stays at or above 8 V with VDD at its 5.000 V minimum; the LDO feeding the inverter guarantees 3.2505 V minimum, leaving 250.5 mV for the inverter's loss and ripple at a load in the microamp to low-milliamp range. If no bound exists, please say so and we will measure it.

If the drain must stay within VFP + 0.7 V at all times, we would appreciate TI's recommended approach: for example a Schottky from Dx to VDD, keeping VDD ungated and gating something else, or a different part in the family that specifies the drain side when unpowered.

Thank you,

Jiahui

RE: TMUX7462F: TMUX7462F: drain pin absolute maximum (VFP + 0.7 V) vs. drain levels blocked when powered off

Nir Gilgur — Tue, 03 Nov 2026 18:56:26 GMT

Hello Jiahui,

1. There is no fault protection on the drain pins, only on the source pins. The page 4 statement is correct about the drain pins and the statement on page 26 is only for the source pins.

2. There is an ESD diode on the drain side, so if you exceed the rating you will reverse bias the diode and back power the device. Since you are limiting the current to be below 1mA this shouldn't be an issue.

3. The device is guaranteed off at 0V and on at 8V, anything in between is undefined.

4. We don't, the only information we have is what is in the datasheet

For questions 5 to 9, we don't have information for such cases. I recommend referencing the overvoltage leakage graphs on pages 16 and 17.
Another option is for the customer to test the parts themselves in these specific cases.

10. I don't support the TPS part, let me loop in the right team.

We recommend the drain to stay within recommended operation conditions.
The VFP + 0.7 V specification is a stress conditions and shouldn't be followed.

A Schottky, or even a diode will work.
Overall, if you limit the current below the source or drain continuous current spec, you should be fine without an external component on the drain side.

Thanks,

Nir

TS5A3159A: TS5A3159A: input signal isolation in power-down mode

Daniel Ka — Tue, 03 Nov 2026 16:52:48 GMT

Part Number: TS5A3159A

Hello,

the datasheet for the TS5A3159A Analog Switch claims the feature "Isolation in Power-Down Mode, V+ = 0".

What does that mean for the analog input signals?

The absolute max. ratings on page 4 limit the analog input voltage to (V+) + 0.5 V. With V+ = 0 that would be only 0.5 V.

I think that contradicts data in the power-off rows (e.g., I_NC(PWROFF)) which characterize input signals up to 5.5 V with the chip unpowered to exhibit leakage currents in the µA regime. I assume that if there were ordinary protection diodes from the signal pins to V+, an unpowered chip with 5 V on a pin would conduct milliamps, not µA.

Can I apply 5V to the input pins when the chip is unpowered?

Thanks.
Daniel

TMUX646EVM: SCHEMATIC FOR TMUX646

ROSHAN RAJAGOPAL — Thu, 15 Oct 2026 11:19:34 GMT

Part Number: TMUX646EVM

Hi ,

We are currently developing a custom board based on the TI AM62P processor and are considering using the TMUX646 in our design.

Could you kindly provide us with a downloadable PDF version of the schematic? Having the schematic in PDF format would make it easier for us to review the circuit details and make the necessary modifications for our custom board, rather than referring to the schematic screenshots available in the user manual.

Regards,
Roshan Rajagopal

RE: TMUX646EVM: SCHEMATIC FOR TMUX646

ROSHAN RAJAGOPAL — Tue, 03 Nov 2026 04:11:16 GMT

Hi Nir,
Thank you for the reply , waiting for the AM62P team to comment on this so that we can proceed with the design and decide for pullup or not.

Regards,
Roshan Rajagopal

RE: HD3SS3220: HD3SS3220: USB 3.0 works in only one Type-C orientation; DIR remains high in both orientations

Katy West — Mon, 02 Nov 2026 20:55:21 GMT

Hi David,

I understand your main concern - my questions are to help get to the root of the issue here. It is clear that the CC1/CC2 pin voltages are incorrect and because of this, ID pin is not being pulled low, so VBUS cannot work properly.

Looking at just the schematic again, the only potential issue I am seeing is that the AC coupling capacitors - they are out of our recommended range of 75nF to 200 nF. Please replace them with appropriately sized capacitors and let me know if that fixes the issue. If the issue persists, please monitor the voltage on the ID pin and let me know what you see in each circumstance.

I2C mode settings should not affect the ability of the MUX to control/ recognize the proper orientation.

Best,
Katy

HD3SS3220: HD3SS3220: USB 3.0 works in only one Type-C orientation; DIR remains high in both orientations

Ryan Hsu — Thu, 29 Oct 2026 02:58:29 GMT

Part Number: HD3SS3220

Hi TI Team,

We are supporting a customer using the HD3SS3220 in an AI BOX design. A directly connected SanDisk USB Type-C flash drive works at USB 3.0 speed in one plug orientation, but only at USB 2.0 speed when flipped.

Please help review the following configuration and measurements.

Hardware configuration

PORT (pin 4): Pulled high for fixed DFP mode.
ENN_CC (pin 29): Pulled low through a 10 kohm resistor.
ENN_MUX (pin 12): Pulled low through a 10 kohm resistor.
DIR (pin 11): Pulled up to 3.3 V through a 200 kohm resistor.
CC1 and CC2: Connected to the Type-C connector through the TPD6S300A.
ADDR (pin 22): Configured for I2C mode.
TPD6S300A VPWR: 3.3 V.
All four TX AC-coupling capacitors, 220 nF each, are populated.

Measurement results

Without a device connected:

CC1: Approximately 4.75 V.
CC2: Approximately 4.75 V.
DIR: 3.3 V.

With the flash drive connected in Orientation A:

CC1: Approximately 0.9 V.
CC2: Approximately 0.8 V.
DIR: 3.3 V.
USB 3.0 operation: Pass.

With the same flash drive flipped to Orientation B:

CC1: Approximately 0.9 V.
CC2: Approximately 0.8 V.
DIR: 3.3 V.
USB 3.0 operation: Fail. USB 2.0 still works.

Additional observations:

The flash drive is connected directly, without a cable or adapter.
Similar CC voltage levels were measured on both sides of the TPD6S300A.
No short circuit was found between CC1 and CC2.

Questions

A. In fixed DFP mode, what CC1 and CC2 voltage levels should we expect before and after attachment in each plug orientation? Is it expected for both CC pins to drop to approximately 0.8 to 0.9 V simultaneously with this directly connected flash drive?

B. Should DIR change when the flash drive is flipped? Since DIR remains at 3.3 V in both orientations, what checks would you recommend to verify orientation detection?

C. With ADDR configured for I2C mode and PORT fixed to DFP, does the HD3SS3220 automatically detect the plug orientation and switch the SuperSpeed MUX after power-up? Is any I2C register initialization required? If so, please provide the necessary settings and sequence.

D. Which registers and bit fields should we read to verify attachment status, detected plug orientation, and MUX selection, if available? What values should we expect in each orientation?

We would appreciate your guidance on verifying the CC detection and MUX switching behavior, as well as any additional hardware checks you recommend.

Best regards,
Ryan Hsu

RE: TMUX646EVM: SCHEMATIC FOR TMUX646

Nir Gilgur — Mon, 02 Nov 2026 17:55:21 GMT

Hello Roshan,

1. I see, no you don't have to connect the pull ups. The EVM provides that option for evaluation flexibility.

2. Looping in the team.

Thanks,

Nir

RE: TMUXHS4446: Adaptive CMV tracking and application

Katy West — Mon, 02 Nov 2026 15:24:56 GMT

Hi Thaituan,

I am from the multiplexer team, so cannot comment on this. Please reach out to the appropriate TI team for advice.

Best,
Katy

TMUXHS4446: Adaptive CMV tracking and application

THAITUAN TRAN — Wed, 28 Oct 2026 05:21:58 GMT

Part Number: TMUXHS4446

Hi team,

I am currently designing a DisplayPort system with the following topology:
DP Source > TMUXHS4446 > AC cap > TDP142 > AC cap > Type-C Connector
Please review this architecture and clarify the following points for me:

1. In the event that an AC-coupling capacitor is added between the DP Source and the TMUXHS4446, will I need to implement an external Vbias termination network? If so, on which side of the TMUXHS4446 should it be placed?

2. Regarding the TDP142, does it feature an internal Vbias termination network on its input side? If yes, what is the exact common-mode voltage (Vcm) value, and does it fall within the TMUXHS4446's acceptable input range of 0V to 1.8V?

3. If the internal Vbias of the input side TDP142 lies within the compatible range of the TMUXHS4446, can I safely eliminate the AC-coupling capacitor between them? Instead, I will add an AC-coupling capacitor between TMUXHS4446 and the DP source.

4. I am searching for a suitable USB PD Controller for this specific architecture, but it appears that most legacy options are marked as NRND (Not Recommended for New Designs). Do you have any active product recommendations?

RE: TMUX646EVM: SCHEMATIC FOR TMUX646

ROSHAN RAJAGOPAL — Mon, 02 Nov 2026 04:31:19 GMT

Hi Nir,

I don't mean to leave it floating, I mean in the evm schematic there is pull up and pull-down resistors, do we need to connect the same after connecting them to the processor?
Yes, it would be helpful if you can loop them in this thread too.

Regards,
Roshan Rajagopal

LM5146: variable 10 V - 200 V 1MHz pulse generator request

Jacob Newman — Fri, 30 Oct 2026 11:47:46 GMT

Part Number: LM5146

I'm looking for a pulse generator suitable for applying a voltage of between 10V and 200V to a 30mm long metal cylinder with a 10mm aperture, held between (but entirely insulated from) two grounded cylinders of identical shape and size. This setup will be held under high vacuum. Other than the voltage, the pulses must fit the following profile:

- Minimum 1MHz repetition rate in continuous mode
- 50% duty cycle (square wave with minimal [<100ns] rise and fall times)
- Pulse width of 500ns

Is anyone able to advise if TI have a product suitable for this application?

RE: LM5146: variable 10 V - 200 V 1MHz pulse generator request

Pramanik Patel — Mon, 02 Nov 2026 02:19:23 GMT

Hi,

LM5146 is a buck device and seems not a good fit for pulsd generation. Please raise a E2E with proper tag. By then I will check internally which team can support this.

Thanks

RE: TMUXHS4446: Adaptive CMV tracking and application

THAITUAN TRAN — Mon, 02 Nov 2026 00:14:39 GMT

Hi Katy,

Thanks for the answer.

Now i am looking for a PD controller with DP alt mode supporting. Do you have any suggestion?

Regard.

RE: HD3SS3220: HD3SS3220: USB 3.0 works in only one Type-C orientation; DIR remains high in both orientations

david su — Fri, 30 Oct 2026 20:40:55 GMT

HI Katy:

Thank you for your support.

To clarify our main concern, the same USB-C flash drive operates at USB3.0 in one orientation but only at USB2.0 in the opposite orientation. DIR remains High in both orientations. We would therefore like to focus on the CC orientation detection and automatic SuperSpeed MUX switching mechanism.

Our current configuration and observations are:

U33 is configured as DFP through the PORT pin, and its power supplies are normal.
ADDR is configured for I2C mode. However, I2C communication with the SoC has not yet been established, so we are relying on hardware settings and power-on defaults.
To answer your question, ID is currently connected only to a pull-up resistor and a test point; it is not connected to the SoC.
Before insertion, CC1 and CC2 are both approximately 4.75V. After insertion, both become approximately 0.98V, regardless of plug orientation.

Could you please clarify the following points?

Hardware requirements and the role of ID
Which hardware pins and conditions are required for automatic orientation detection and internal MUX switching? Does connecting ID to the SoC affect CC/DIR operation itself, or is this connection used to notify the SoC to control VBUS after attachment has been detected?
I2C mode without I2C communication
With ADDR set to I2C mode, should CC1/CC2 detection, DIR output, and automatic MUX switching operate without any I2C initialization? Could selecting I2C mode without establishing communication cause the behavior we are observing? If initialization is required, please specify the registers, values, and sequence.
Hardware-only verification
With U33 normally powered and connector VBUS held at 0V before attachment, should orientation detection work while ID is connected only to its pull-up? Would you recommend changing ADDR to GPIO mode for this test? If so, please provide the required pin configuration.

We understand that VBUS must be controlled correctly. Our immediate question is whether U33 can autonomously detect orientation and switch the MUX under the configuration above.

Best regards,
David

RE: HD3SS3220: HD3SS3220: USB 3.0 works in only one Type-C orientation; DIR remains high in both orientations

Katy West — Fri, 30 Oct 2026 14:41:01 GMT

Hi David,

Could you confirm what the ID pin is connected to on the other end? Is it connected to the SOC? Or is it only connected to the pull-up I see in the schematic you shared? The ID pin is what should be pulled low to trigger VBUS being sent through the connector, not the other way around. The ID pin needs to be connected to that of the SOC.

Best,
Katy

RE: TS3USB221A: Internal Pin Lengths

Katy West — Fri, 30 Oct 2026 14:24:35 GMT

Hi Shane,

The internal pin length is TI information, so unfortunately, I cannot share this. However, you can see all of the external lengths in the package drawing for this device at the end of the datasheet.

Best,
Katy

TS3USB221A: Internal Pin Lengths

Shane Kirkpatrick — Fri, 30 Oct 2026 11:53:57 GMT

Part Number: TS3USB221A

Can you provide the interal pin lenghts for TS3USB221ARSER that support the USB interface(s).

RE: TMUXHS4446: Adaptive CMV tracking and application

Katy West — Fri, 30 Oct 2026 14:15:48 GMT

Hi Thaituan,

Yes that is necessary if the host or endpoint devices combined with the AC coupling caps have a common mode voltage that doesn't match that of the TMUXHS4446.

Best,
Katy