Switches & multiplexers forum - Recent Threads

HD3SS3220: Power consumption & schematic review

Sathya N — Tue, 11 Aug 2026 04:40:04 GMT

Part Number: HD3SS3220

Hi Team,

Currently in our design we are using the PD controller TPS25751, USB mux HD3SS3220 & Battery charger BQ25750 . In my design the type c will act as host as well as device, and charging the batetry.

- Kindly provide the detailed power consumption of- HD3SS3220 VC33 - 0.9 mA?, VDD5 - ? for our scenerio.

- In MUX - For our scenerio Where to connect the VBUS_DET and ID pin.

RE: HD3SS3220: Power consumption & schematic review

Sathya N — Fri, 04 Sep 2026 10:04:29 GMT

Hi Team,

As discussed we are using the TMUXHS4212, Whether the pin 1 and 10 RSVD should be left floating or should i tie to VCC. datasheet says to tie to VCC and EVM is just TP. Kindly confirm.

Datasheet

EVM

checklist:

TMUXHS5212: Whether use TMUXHS5212 with UFS4.0 interface?

Duoc Nguyen — Fri, 04 Sep 2026 03:33:56 GMT

Part Number: TMUXHS5212

Hi TI team

I am trying to find the analog MUX which support UFS4.0 interface. I see TMUXHS5212 can work upto 32Gbps ( UFS4.0 23.32Gbps ). But in application of TMUXHS5212 does not mention UFS interface.

Can you check about my concern?

If TMUXHS5212 can work with UFS4.0, could you share S-Para model for us to simulate?

Thanks,

Duoc

SN74CB3T3257: S pin max switching frequency / tBBM

Danilo A. — Fri, 28 Aug 2026 21:11:20 GMT

Part Number: SN74CB3T3257

Hi Team,

Posting on behalf of our customer.

ontext: I'm evaluating SN74CB3T3257 to time-division-multiplex a 4-bit bus between two devices, with the S select pin toggling at a relatively high rate (in the range of 50-100MHz) to alternate which of the two channels is connected to the bus controller on a per-cycle basis. OE is held permanently enabled in my design and is not part of the high-speed switching path. I need to confirm the S pin specifically can safely support this switching rate without a transient overlap between the two channels during the switch transition.

Questions:

A maximum switching frequency for the S pin does not appear to be listed in the public datasheet's Switching Characteristics table — is there a characterization or recommended value that could confirm a safe operating point for a TDM application like the one described above?
Is there a guaranteed break-before-make time (tBBM) for the S-controlled channel transition — i.e., a guarantee that the previously selected channel is fully disconnected before the newly selected channel connects? This would help confirm there's no momentary overlap between the two channels during switching.
For additional context: what is the internal switching mechanism used by SN74CB3T3257 to drive the pass-transistor gates in response to the S input? The datasheet describes "voltage translation that tracks VCC" — could you clarify whether this involves any active gate-boost circuitry (e.g., a charge pump) or a simpler passive mechanism?

Regards,

Danilo

RE: SN74CB3T3257: S pin max switching frequency / tBBM

Danilo A. — Thu, 03 Sep 2026 22:49:46 GMT

Hi Nir,

Thank you for the detailed clarification that the CB3Q/CB3T charge-pump architecture has an inherent ceiling around 10MHz in the worst case. At room temperature the limit is presumably higher, but probably still well short of what my unusual design needs.

To answer your question:

Goal: to demonstrate that two autonomous, mutually isolated peripherals can work at the same time without interfering with each other, by simply deriving two separate headers from the same physical 8-bit bus and multiplexing at double the peripherals' native frequency, rather than dedicating a separate set of FPGA pins to each one, given that the devices latch values on the clock rise/fall.

Application: in my design the FPGA has very few free I/O pins available, but needs to drive two peripherals -- each operating at 50MHz -- effectively at the same time. The approach relies on time-division multiplexing: the shared bus toggles at 100MHz, with latches at the start of each clock cycle on the peripheral side capturing the correct data window.

At this point, I'm evaluating charge-pump-free alternatives such as the simple CMOS pass-gate SPDT switch SN74LVC1G3157. Its datasheet shows a guaranteed break-before-make of 0.5ns and ten/tdis around 7.6ns/5.3ns at VCC=3.3V (worst case, 85C). Since this part doesn't rely on an internal charge pump, it doesn't appear to carry the same recharge-time limitation you described for CB3Q/CB3T. Based on the datasheet numbers alone, this points to a realistic operating ceiling in the 60-65MHz range under worst-case conditions, with headroom toward ~80MHz at room temperature and a lighter real-world load than the 50pF test condition.

I did not find an 8-channel device that offers similar performance for my needs.

I really appreciate you taking the time to help me in my research.

Regards,

Danilo

RE: TS5A3157: CCOM maximum capacitance

Joe Miller1 — Thu, 03 Sep 2026 21:12:05 GMT

Hi Arya,
Thank you.
Regards Joe

TS5A3157: CCOM maximum capacitance

Joe Miller1 — Fri, 28 Aug 2026 11:39:10 GMT

Part Number: TS5A3157

Dear Sir/Madam,

I am looking for a single supply analog switch that has less than 30pF maximum capacitance.
The image below illustrates what I am tryinto do. The VSET/VID pin need to have less than 30pF capacitance. Basically less than 30pF on the COM pin to GND when the switch is connected COM to NC or COM to NO. The TS5A3157 specifies Cno(on)/Cnc(on) as 17.5pF (typ) and ccom(on) as 17.5pF typ. Does this mean that if the switch is on and COM is connected to NC the the capacitance seen at the com pin is 17.5pF + 17.5pF (35pf) or just 17.5pF? What is the maximum capacitance values? If TS5A3157 the is not suitable what part would you recommend?

Regards Joe

TS3L501E: S Parameter model needed - TS3L501E

Thanga Prabu Suyambukasi — Thu, 03 Sep 2026 06:43:46 GMT

Part Number: TS3L501E

Hi Team!

Could you please provide the S Parameter model for the IC (TS3L501E ). We need it urgently for our SI simulation. kindly support us

Thanks,

Prabu

RE: TS3L501E: S Parameter model needed - TS3L501E

Nir Gilgur — Thu, 03 Sep 2026 14:50:25 GMT

Hello Prabu,

Unfortunately, we don't have an SP model for this device.
Currently, our best solution is for you to create one using passive components as explained here.

Thanks,

Nir

SN3257-Q1: SN3257-Q1 support the I2C MUX ?

dean.yao — Thu, 03 Sep 2026 03:39:17 GMT

Part Number: SN3257-Q1

can the SN3257-Q1 support the I2C MUX ?

thanks

RE: SN3257-Q1: SN3257-Q1 support the I2C MUX ?

Nir Gilgur — Thu, 03 Sep 2026 14:44:18 GMT

Hello Dean,

Do you mean can the SN3257-Q1 support I2C muxing?
If so, the answer is yes.

Thanks,

Nir

RE: ULN2003ADYYEVM: ULN2003ADYYEVM

Patrick Shalton — Thu, 03 Sep 2026 03:43:02 GMT

Hi Jason,

These external pull-down resistors can help eliminate spurious switching in very noisy environments. However, they typically are not needed because the device has internal pulldowns, as you mentioned.

Thanks,

Patrick

ULN2003ADYYEVM: ULN2003ADYYEVM

Jason Williams71 — Mon, 31 Aug 2026 15:39:56 GMT

Part Number: ULN2003ADYYEVM

Hello, Why does the ULN2003ADYYEVM have 10k pull-downs on each input when the ULN2003ADYY already has 7.2k and 3k resistors connected between the input base and emitter of each respective NPN channel? What added benefit do they provide?

Thank you

TS5A23166: Supply Current

Takashi Imai — Mon, 31 Aug 2026 02:33:01 GMT

Part Number: TS5A23166

Hello,

I have received the following inquiry from our customer regarding the supply current of the TS5A23166DCUR. Could you please assist me with the response?

The customer reports that the supply current (I+) is approximately 5mA under the following operating conditions.
V+ pin: 5.5 V
IN1 / IN2: 3.3 V
NO1 / NO2: 0.14 V to 1.5 V, source output impedance = 200 kohms
COM1 / COM2: Connected to the MCU ADC input, input resistance = 2.5 kohms

The customer also reported that, as a trial, increasing the IN1/IN2 voltage from 3.3 V to 5.5 V reduced the supply current to less than 0.1 µA.

I have received the following two questions from the customer. Could you please advise?

What could be the possible cause of the increase in supply current (I+) to approximately 5 mA when IN1/IN2 are set to 3.3 V?
The assumption is that, because the CMOS input voltage is at an intermediate level relative to the supply rails, the internal PMOS and NMOS transistors are simultaneously conducting, resulting in increased shoot-through current. Is it possible that this is what's occurring internally?
The datasheet specifies that VI should be set to the same voltage as IN1/IN2 when measuring Supply Current. Are there any disadvantages if VI is not set to the same voltage as IN1/IN2?
For example, could this result in device reliability concerns, excessive power dissipation, loss of analog switch functionality, increased supply current, or even device damage due to excessive internal current?

Thanks & Regards,
T.Imai

RE: TS5A23166: Supply Current

Nir Gilgur — Wed, 02 Sep 2026 17:23:05 GMT

Hello Imai-san,

My point was that they are actually might not be in the threshold levels.
The datasheet doesn't specify at what V+ level the 2.4V threshold is.

My theory is the 2.4V threshold is actually for V+ = 4.5V.
Since the customer is operating at V+ = 5.5V, 3.3V on the IN pins is not enough.

Great! Please share with me their findings when you get them.

Thanks,

Nir

RE: SN74CB3T3257: S pin max switching frequency / tBBM

Nir Gilgur — Wed, 02 Sep 2026 17:07:38 GMT

Hello Danilo,

1. Yes, the switching frequency is 10MHz max due to the temperature being 105C. If your application is at 25C (room temp) then the limit will be higher, but I don't have the information to how high. Switching frequency is not a common specification we mention in our datasheet. I wouldn't be surprised if the SN74CB3Q3257 device is the only one that has it.
Also, I would say the SN74CB3Q3257 is the better choice here since it has slightly faster switching timings, though I cannot confirm if it will be fast enough for your application.
Our CB3Q and CB3T product families are considered to be our fastest switching muxes, so unfortunately I don't think we have a better option to recommend.

2. My assessment was pretty simple, I converted the 100MHz frequency into a period which comes out to be 10ns. I didn't take the cadence into account.
Can you elaborate more on why you are trying to switch the channels so quickly? This is quite a unique use case.

Thanks,

Nir

TMUX7234: Plateau at fast rising edge

Nikolas Zingraf — Thu, 25 Jun 2026 13:56:28 GMT

Part Number: TMUX7234

Hello,

I am having an issue with is the TMUX7234 -SSOP20 (www.ti.com/.../TMUX7234). We use this component to isolate a total of 4 analog outputs from the output connector. For this purpose, one input (Port A) is connected to the analog signal, and the second (Port B) is connected to the ground potential.

We have now found that with steep edges of about 1 V/µs on Port 4A, all outputs are pulled to ground (see image Plateau_AOUT1_10kOhm). In this image, the yellow curve represents the output of the first channel on the TMUX7234 (which should remain static at 10 V), and in green, you can see the output of the fourth port, which jumps from -10V to +10V. Since the steepness of the signal on Port 4 is greater than 1 V/µs, the TMUX7234 generates a plateau of about 20 µs that affects all outputs simultaneously. This behavior only occurs when the jump happens on the fourth port and only on the rising edge. We have already disconnected the circuit before the TMUX7234 and fed it directly with a signal generator, resulting in identical behavior.

Additionally, we have increased the decoupling capacitors of the power supply without improvement. Therefore, we strongly suspect that the TMUX7234 is causing this behavior. Furthermore, we have observed that the steeper the edge, the earlier (closer to 0 V) the plateau occurs (compare image (6) and image (7)). Another test on input 4B yields the following result (see image (8)).

We have also seen that even with very steep falling edges, all input ports likely exhibit a slight “glitch” (see image (9) = steep falling edge at input 1B and image (10) = steep rising edge at input 1B).

The marking on the tested ICs is: T234 TI53K A75T

Are you familiar with such behavior? In our application, this is a very undesirable behavior, especially that Port 4A is so easily disturbed.

Plateau_AOUT1_10kOhm:

image (6)

image (7)

image (8)

image (9)

image (10):

RE: TMUX7234: Plateau at fast rising edge

Arya Hussein — Wed, 02 Sep 2026 13:42:30 GMT

Hi Nikolas,

I am getting more samples and there was a shipping delay. So in the mean time I wanted to look at your schematic to see if there was anything that stood out.

Also does this happen for sine waves or any other wave form?

Thank you,
Arya

RE: TS5A23166: Supply Current

Takashi Imai — Wed, 02 Sep 2026 08:03:24 GMT

Hi Nir-san,

Thank you for your reply.

The customer would like to understand why the supply current increases when the IN pin voltages are within the specified logic threshold levels (VIH/VIL) and the maximum input voltage rating of 5.5 V, even though the IN pins are not required to be driven to the same voltage level as V+.

The customer has confirmed that the supply current decreases to below 0.1 µA when the IN pin voltages are raised from 3.3 V to 5 V.

As request, I will ask the customer to measure the supply current while increasing the voltages on both IN pins from 3.3 V in 0.1 V steps.

In addition, I will ask the customer to perform an additional check by lowering V+ from 5.5 V to 4.0 V while keeping IN1/IN2 at 3.3 V, and confirm how the supply current changes.

Thanks & Regards,

T.Imai

RE: TMUX7234: Plateau at fast rising edge

Nikolas Zingraf — Wed, 02 Sep 2026 05:38:31 GMT

Hi Arya,

I will look for the request. Were you able to confirm that S4A is also not affected?

Regards,

Nikolas

RE: SN74CB3T3257: S pin max switching frequency / tBBM

Danilo A. — Tue, 01 Sep 2026 20:54:50 GMT

Hi Nir,

Please see our customer's response below.

Thank you for the quick and detailed response — much appreciated.

I have two small follow-up questions to make sure I understand correctly.

I was previously also considering the SN74CB3Q3257 for my design, since it initially seemed like a better fit, with a nominally much shorter switching time. However, I then found that it has an explicit maximum control-input switching frequency (fS) of 10–20MHz documented in its datasheet. Since, as you explained, it shares a similar charge-pump/gate-driver architecture with the CB3T3257, and the CB3T3257 datasheet doesn't mention an equivalent limit, I wanted to be sure a similar consideration could not apply here (a difference between the two designs would easily explain it).

Separately, on your point about switching times at 100MHz (~10ns) being fine: I wanted to check one detail about my specific use case. I'm using the device for time-division multiplexing with S driven by a square wave at 100MHz, so the channel select toggles every half-period, i.e. every 5ns, not every 10ns. Could you confirm whether your assessment already took this 5ns cadence into account, or whether it was based on the full 10ns period?

Thanks again for your help — I really appreciate you taking the time to look into this.

Regards,

Danilo

TMUX1204: Schematic Review

Tilden Chen — Mon, 31 Aug 2026 21:23:03 GMT

Part Number: TMUX1204

Hello Mux Team,

I'm an applications engineer from DLP team developing an EVM featuring your device, TMUX1204. Using the mux to select between different DAC outputs, up to 20 kHz, and connected to ADC input. Please let me know if you have any suggestions to improve the schematic.

Schematic - p67 PLM EVM - DLP135.pdf

RE: TMUX1204: Schematic Review

Nir Gilgur — Tue, 01 Sep 2026 18:24:54 GMT

Hello Tilden,

Schematic looks good! No issues at all.

We don't specify quiescent current frequency for any of our parts.
The closest spec we do have is current supply, please see below:

Thanks,

Nir

RE: TS5A23166: Supply Current

Nir Gilgur — Tue, 01 Sep 2026 17:38:03 GMT

Hello Imai-san,

I see, they are correct.
The IN pins don't have to be operated at the same level as V+.

As long as they are operated according to the logic thresholds (VIH and VIL) as well as within spec (up to 5.5V) there shouldn't be any issues or concerns.

This seems like a shoot through event, but it occurs when the voltage on the control pins is below VIH and above VIL (outside of spec).
They are inputting 3.3V which is way above the logic high threshold of VIH of 2.4V.

Though the datasheet doesn't specify the V+ level for the 2.4V spec. It only mentions at the top of the page the voltage range of 4.5V to 5.5V.

So, my theory is that the 2.4V VIH threshold is probably for a 4.5V supply and for a V+ of 5.5V it will be higher.
To confirm this, can the customer ramp up the voltage signal on the IN pins till the current goes down?
Meaning start at 3.3V on both pins and go up in 0.1V steps until the current level is reduced?

Yes, with the increased current there will be an impact on device reliability and longevity.
I recommended operating the IN pin either on the V+ voltage level of 5.5V.

Thanks,

Nir

TS3L501E: Need IBIS/SPICE model for this TS3L501E Part

Rajesh Ketharaju — Tue, 01 Sep 2026 07:20:25 GMT

Part Number: TS3L501E

Hi,

I'm looking for SPICE/IBIS model for TS3L501ERUAR part number. whichever is available you can share it.

Thanks,

Rajesh.