https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1695407/sn74cb3q3251-sn74cb3q3251pw-junction-to-board-jb-thermal-resistanceWed, 04 Nov 2026 20:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b20950d4-c4b1-4756-b4b9-1408ee5498e7Zachery CheungPart Number: SN74CB3Q3251 I looked at the datasheet for SN74CB3Q3251PW and could only find the Junction-to-Ambient (JA) value. I require the Junction-to-Board Thermal (JB) resistance value for thermal analysis. Can you please share this information with me, if it is available? Thank you, ZachSN74CB3Q3251https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1695024/ts5a3159a-ts5a3159a-input-signal-isolation-in-power-down-mode/6530539Wed, 04 Nov 2026 18:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ede98bfb-407c-40c2-bcc1-85ac86f99fc6Nir GilgurHello Daniel, Unfortunately, we currently don&#39;t have the bandwidth but it is in our backlog to do so. Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694867/hd3ss3220-hd3ss3220irnhr-not-working/6530525Wed, 04 Nov 2026 17:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3903ffde-dbf9-4dc3-aaeb-3d8ff73dca0bNir GilgurHello Jay, You don&#39;t need to replace all the AC caps with 0R, that will not work. Just remove C247 and C253 and the ones on the TX side should remain. Also, thank you for sharing the PDF version. I can see their values is 0.22uF, which is above the allowed range. I recommend implementing 100nF capacitors instead. Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1689269/tps62932-selecting-the-right-component/6530133Wed, 04 Nov 2026 11:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:09327251-c52a-464a-a410-9bf846a4e419Teja RowthuHi Gael, We have two options for handling such usecase based on the cost, speed and switching type you are targetting. Sitara AM243x/AM64x Solution: AM243x and AM64x SoCs can support upto 5 ethernet ports. These consist of two independent switches, and one independent MAC port (Although, internally, they are 3 independent 3-port switches). We need to employ SW switching to transport the packets between the switches, and to implement the Splitter logic. This would mean, the maximum throughput which can be supported is limited to around 100 Mbps, even though the individual ports can support 1Gbps. This is the relatively mode budget oriented solution Jacinto J7/TDA4 solution: Jacinto platforms support upto CPSW 9G, which have 8 external MAC ports and an internal Hostport, and can be configured into a splitter/merger configuration. There are also options with CPSW 5G, where there are 4 external MAC ports, and one host port. This is completely HW based switching and can support upto 1Gbps switching speeds. This is a hgher end solution with higher pricing as well as more compute compared to Sitara offerings. Please let us know which solution you are looking towards, and we can support you to identify the better fit to your application and requirement. Thanks and regards, Teja.https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694733/tmux7462f-tmux7462f-drain-pin-absolute-maximum-vfp-0-7-v-vs-drain-levels-blocked-when-powered-off/6530044Wed, 04 Nov 2026 09:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:63096b58-d2c2-4e09-9e84-fa712e628ca3Andreas MuellerHello Jiahui, I&#39;m supporting the TPS devices... Please be aware that the TPS60403 is an unregulated inverter. Basically it generates Vout = -Vin, whereby the output voltage drops a bit with load due to losses in the switches and in the capacitors ESR. This means: For the mentioned case of +5 V LDO supply of the TPS60403 you will get approximately VSS = -5 V at its output (without load). The losses and with this the output voltage drop towards GND are depending on the ESR of the flying cap and the output cap you chose for this application (see equation 2 on page 11 of the datasheet ). A typical output voltage range at 3.3 V input voltage is shown below: From your comments it seems that 10 mA would be the worst case load condition. For Vin = 3.3 V and Iout = 10 mA the data points of the plotted output voltages would be Vout = -3.1888 V at 85 &#176;C, -3.1992 V at 25 &#176;C and -3.2036 V at -40&#176;C. For the voltage drop this means 111.2 mV at 85 &#176;C, 100.8 mV at 25 &#176;C and 96.4 mV at -40 &#176;C. I think ca. 30 mVpp of ripple can be assumed at 10 mA load. So, the mentioned 250.5 mV headroom should be sufficient to cover for voltage drop + ripple. Please pay special attention to low ESR of the capacitors. Please refer to table 9-2 in the datasheet for recommended capacitor types. If you need a regulated inverter for maintaining VSS = -3 V in the condition of +5 V supply then the LM27761 could be evaluated. The remaining headroom for the +3.2505 V supply case might be a bit tight for maintaining -3 V output voltage with the LM27761. Unfortunately I don&#39;t have any measurement data for this case. A third alternative would be a buck converter, operated in inverting buck-boost configuration. Such application should be able to maintain a regulated -3.3 V output voltage for a wide range of input supply voltage. Here is some collateral, explaining more details: &quot; Using the TPS62120 in an Inverting Buck-Boost Topology &quot;. Let me know if you have any questions. Best regards, Andreas.https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1695024/ts5a3159a-ts5a3159a-input-signal-isolation-in-power-down-mode/6529990Wed, 04 Nov 2026 09:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b2ccb7cd-5d74-44a0-b1fc-ce3cfbb6ee1bDaniel KaCould you please update the datasheet accordingly? It hasn&#39;t been updated in eight years.https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694867/hd3ss3220-hd3ss3220irnhr-not-working/6529654Wed, 04 Nov 2026 02:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bb4c6ad7-6e4d-43a4-934f-52639ed4dcabjay CarloHello NIR, Yes DIR was pull up with 200K. Replace all TX and RX input with 0R still does not enumerate. e2e.ti.com/.../USB3.1.pdfhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1693238/tmuxhs4446-adaptive-cmv-tracking-and-application/6529598Wed, 04 Nov 2026 01:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2707ebe1-0c6b-40f1-81eb-2291d60d68a4THAITUAN TRANHi Katy, Thank you for supporting. I am waiting the respond for TDP142. Regard.https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1695024/ts5a3159a-ts5a3159a-input-signal-isolation-in-power-down-mode/6529370Tue, 03 Nov 2026 21:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b73799b5-1a34-407a-bded-eede26ab47f4Nir GilgurHello Daniel, This feature indicated that when the supply pin V+ = 0V, you can have voltage present on the I/O pins without the risk of back powering the device. Though, for the TS5A3159A this is a typo, it doesn&#39;t have this feature . You cannot apply 5V on the input pins when the device is unpowered. The datasheet has a typo mistake and the information on page 4 is correct. I would recommend the TMUX2819 here instead. It can support your application. Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694968/tmux7612-tmux7612-maximum-continuous-switch-current-with-multiple-channels-on-simultaneously/6529332Tue, 03 Nov 2026 20:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1149b48c-db6b-4929-83b2-0b592518c9ecNir GilgurHello Gilbert, 1. The 470mA specification is per switch. You can have all channels enabled with each one carrying 470mA of current at the same time for a total of 1.88A. 2. Yes. 3. No, this rating is for all channels passing this current without any additional restrictions. Though, note the device will get hotter and performance will be affected according to that (Ron and current leakage). 4. The 470mA spec is for all four channels enabled at the same time. We also have a thermal calculation guide here . The TMUX7612 can support your application since not a single channel is passing current higher than 470mA. Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694867/hd3ss3220-hd3ss3220irnhr-not-working/6529277Tue, 03 Nov 2026 19:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e86bb8f5-6ce3-45db-a514-70d6d023702cNir GilgurHello Jay, It sems like the schematic was posted in way where if I zoom in it becomes very blurry, but I do have a couple of comments. I don&#39;t see a 200k pull up resistor on the DIR pin. Can you confirm it is implemented? The AC coupling is not implemented correctly. I recommend removing the capacitors on the RX pins, they are not needed. A good rule of thumb is to AC couple the TX or RX lane, not both. Can you share a PDF version of the schematic? Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694814/sn74cb3q3345-vqfn-package-information/6529270Tue, 03 Nov 2026 19:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:aebd02d8-565d-428f-9183-cb041ef4815aNir GilgurHello Jeff, See package details below. e2e.ti.com/.../4225320.pdf Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694733/tmux7462f-tmux7462f-drain-pin-absolute-maximum-vfp-0-7-v-vs-drain-levels-blocked-when-powered-off/6529246Tue, 03 Nov 2026 18:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3b8b69b7-0e60-4f7b-9e84-bbd3212ed7fcNir GilgurHello Jiahui, 1. There is no fault protection on the drain pins, only on the source pins. The page 4 statement is correct about the drain pins and the statement on page 26 is only for the source pins. 2. There is an ESD diode on the drain side, so if you exceed the rating you will reverse bias the diode and back power the device. Since you are limiting the current to be below 1mA this shouldn&#39;t be an issue. 3. The device is guaranteed off at 0V and on at 8V, anything in between is undefined. 4. We don&#39;t, the only information we have is what is in the datasheet For questions 5 to 9, we don&#39;t have information for such cases. I recommend referencing the overvoltage leakage graphs on pages 16 and 17. Another option is for the customer to test the parts themselves in these specific cases. 10. I don&#39;t support the TPS part, let me loop in the right team. We recommend the drain to stay within recommended operation conditions. The VFP + 0.7 V specification is a stress conditions and shouldn&#39;t be followed. A Schottky, or even a diode will work. Overall, if you limit the current below the source or drain continuous current spec, you should be fine without an external component on the drain side. Thanks, Nirhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1695024/ts5a3159a-ts5a3159a-input-signal-isolation-in-power-down-modeTue, 03 Nov 2026 16:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4e0eaefa-f145-4a2e-b14d-1104030559c6Daniel KaPart Number: TS5A3159A Hello, the datasheet for the TS5A3159A Analog Switch claims the feature &quot;Isolation in Power-Down Mode, V+ = 0&quot;. What does that mean for the analog input signals? The absolute max. ratings on page 4 limit the analog input voltage to (V+) + 0.5 V. With V+ = 0 that would be only 0.5 V. I think that contradicts data in the power-off rows (e.g., I NC(PWROFF) ) which characterize input signals up to 5.5 V with the chip unpowered to exhibit leakage currents in the &#181;A regime. I assume that if there were ordinary protection diodes from the signal pins to V+, an unpowered chip with 5 V on a pin would conduct milliamps, not &#181;A. Can I apply 5V to the input pins when the chip is unpowered? Thanks. DanielIndustrial AutomationTS5A3159ATMUX2819https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694968/tmux7612-tmux7612-maximum-continuous-switch-current-with-multiple-channels-on-simultaneouslyTue, 03 Nov 2026 13:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1ddde8ce-9b2a-4e95-a3e9-696c8bbf5939Gilbert CabarlesPart Number: TMUX7612 Hello TI Support Team, I am evaluating the TMUX7612 for a high-current analog switching application in our PMU (Parametric Measurement Unit). According to the datasheet, the TMUX7612 specifies a maximum continuous switch current (IDC) of 470 mA at an ambient temperature of 25&#176;C. I would like to clarify how this current rating should be interpreted when multiple internal switches are operating simultaneously. My questions are: Is the 470 mA continuous switch current rating specified per individual switch/channel, assuming only one of the four internal switches is ON? If all four switches are ON simultaneously, can each switch independently carry 400 mA continuously, meaning a total current of 1.6 A distributed across the four channels? If the 470 mA rating is applicable per channel, are there any additional restrictions on the total package power dissipation or maximum allowable current when multiple channels are conducting simultaneously? Does TI provide a derating guideline, thermal calculation, or recommended maximum continuous current per channel when two, three, or all four switches are ON simultaneously? Application details: I am considering using the TMUX7612 in a PMU switching matrix with the following configurations: 500 mA current range: Two switches connected in parallel, carrying approximately 250 mA per switch. 1.2 A current range: Four switches connected in parallel, carrying approximately 300 mA per switch. The objective is to determine whether the TMUX7612 can reliably support these configurations under continuous-current operation, while maintaining the device within its specified electrical and thermal operating limits. I would appreciate your clarification on the current rating interpretation and any thermal considerations for simultaneous operation of multiple channels. Thank you for your support.TMUX7612https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694867/hd3ss3220-hd3ss3220irnhr-not-workingTue, 03 Nov 2026 09:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:81f936fd-bbd4-47e8-8b11-494cb5cc4d56jay CarloPart Number: HD3SS3220 Hello, I have design our custom board using ULPI USB3320 and USB3.1 superspeed TUSB1002RGER and DRP HD3SS3220IRNHR. USB2.0 is working as intended when VBUS is always ON (HW Strap), however, I cannot enumerate USB3.1 when VBUS is controlled by HD3SS3220IRNHR. CC1/CC2 when there is no USB device its 13HZ waiting for device. Once USB Device is plug in CC1 or CC2 is 0.3V. And DIR is High in one direction (0deg) and Low on 180deg USB plug in. There is no Fault as well its high. Voltage 5V and 3.3V are within range. VBUS is normal when a device is plug in VBUS switch is turn ON. TXp/TXn is toggling 170Hz when no USB device is plug in. Not sure why USB3.1 superspeed is not enumerated. Attach is the schematic.Datacom moduleHD3SS3220https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694814/sn74cb3q3345-vqfn-package-informationTue, 03 Nov 2026 07:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:98464b07-5dba-41e2-99f6-bfe75eb6534bJeff YANGPart Number: SN74CB3Q3345 Hi team, Does there have SN74CB3Q3345 VQFN package information? I can&#39;t find it in datasheet. thanks! JeffData center &amp; enterprise computingSN74CB3Q3345https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1689956/tmux646evm-schematic-for-tmux646/6528417Tue, 03 Nov 2026 04:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:77fc7d80-0c73-447d-9fb1-ba213d29a339ROSHAN RAJAGOPALHi Nir, Thank you for the reply , waiting for the AM62P team to comment on this so that we can proceed with the design and decide for pullup or not. Regards, Roshan Rajagopalhttps://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1694733/tmux7462f-tmux7462f-drain-pin-absolute-maximum-vfp-0-7-v-vs-drain-levels-blocked-when-powered-offTue, 03 Nov 2026 02:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c60c08ef-14a9-467b-b29f-2d2654aae7d8Jiahui GaoPart Number: TMUX7462F Other Parts Discussed in Thread: ADS131M08 , , TPS3840 , TPS22918 , TPS60403 , LM27761 Hi team, We are designing a channel protector stage with the TMUX7462F (TMUX7462FPWR, datasheet SCDS394B) in front of a TI ADS131M08 ADC in a power quality meter, and we have questions about the drain pin rating when the part is unpowered or partly powered. Our supply arrangement: - VDD = VFP = +5 V through a TPS22918 load switch with quick output discharge, turned off by a TPS3840 supervisor on the ADC supply. - VSS = VFN = about -3.3 V from a TPS60403 inverter. On one side the inverter is fed by its own TPS7A2033 LDO from +5 V (behind a BAT54 input blocker), so VSS also collapses after +5 V is lost, at the rate its capacitors set. On the other side the inverter shares the ADC&#39;s +3.3 V analog supply, so VSS can stay up after VDD is gone. - DR tied to VDD (drain Hi-Z on a fault). GND connected. - Source: behind external clamp strings with 4.99 kOhm in series; the clamped node stays within about +/-1.5 V in normal use and under faults. - Drain: 2.49 kOhm in series to the ADS131M08 input, 1.2 nF (voltage channels) or 220 pF (current channels) to ground at the ADC pin, and a 100 kOhm bleed to ground. No active source on the drain side. ADC input absolute maximum AGND - 1.6 V to AVDD + 0.3 V, pin current +/-10 mA. With VDD removed and VSS still present, the part sits at VDD = 0 V, VSS = -3.3 V, VDD - VSS = 3.3 V, below the UVLO minimum of 5.0 V (falling), so it is &quot;powered-off&quot; by the definition on page 25. The statements we cannot reconcile: - Absolute maximum ratings, page 4: VD, drain pin (Dx) voltage, VFN - 0.7 V min, VFP + 0.7 V max. With VFP = 0 V that is +0.7 V max on the drain. - Section 8.3.2.2, page 26: &quot;Source and drain voltage levels of up to +/-60 V are blocked in the powered-off condition.&quot; - Page 28: &quot;The voltage on the drain is only allowed to swing between VFP and VFN and no overvoltage protection is available on the drain side.&quot; The case that matters to us: an input fault (+12 V or +60 V behind the clamp) is present while +5 V is lost quickly (a hard short or a 20 us drop). The ADC supply stays up, so the source node sits at about +1.4 V, the channel stays on until VDD - VSS falls through UVLO, and the drain node and its capacitor are left at about +1.3 V while VFP has already fallen toward 0 V. A simulation of an earlier revision showed the drain up to about 0.6 V past VFP + 0.7 V for under 20 us, with drain current in the microamp range, while the bleed and the ADC input discharge it. That is a model result, not a measurement. Questions: 1. In the powered-off condition (VDD = 0 V, VSS = -3.3 V, GND present), which rating applies to the drain pins: the page 4 absolute maximum (VFP + 0.7 V) or the page 26 statement that drain levels up to +/-60 V are blocked? Is the page 26 statement meant for the source pins only? 2. If the page 4 limit applies: what is the failure mechanism on the drain side when VD exceeds VFP + 0.7 V (we assume an ESD diode from Dx to VFP/VDD), and is a short excursion (about +1.3 V on Dx, under 20 us, current limited by the external network to well under 1 mA) acceptable, or must the drain be held within VFP + 0.7 V at all times? 3. Between the UVLO threshold (5.0 to 6.4 V) and the 8 V minimum VDD - VSS in the recommended operating conditions: is the switch guaranteed off, guaranteed on, or undefined? We cross this window on every power-up and power-down. 4. The leakage tables are specified at VS = +/-60 V. Is there any data for source and drain leakage with the supplies removed (or VDD = 0 V and VSS = -3.3 V) and a source voltage of only about +/-1.5 V? Please also answer for each of these cases, for a +/-60 V level on a source pin and for a +/-1.5 V level (the clamped node), giving the guaranteed drain voltage or leakage and the rating that applies: 5. All four supply pins (VDD, VSS, VFP, VFN) at 0 V and grounded; GND present; with DR grounded and with DR tied to VDD. 6. All four supply pins floating (unpowered, no path to ground); GND present. 7. Mixed: VDD = VFP = 0 V grounded with VSS = VFN still at -3.3 V; and the reverse, VSS = VFN = 0 V with VDD = VFP = +5 V (the inverter lost first). 8. Transitions: power-up with the fault already present at the source (VDD rising through UVLO while VDD - VSS is below the 8 V operating minimum), and power-down with the fault present (VDD falling through UVLO, then VSS collapsing). 9. For each case, whether a drain-side pull to a still-powered ADC rail (through 2.49 kOhm, 100 kOhm bleed, 220 pF) violates any rating, and the maximum drain leakage into that node. 10. A related question on the TPS60403 that supplies VSS/VFN: what is its maximum output resistance (or minimum output voltage at a stated load) with VIN = 3.3 V over -40 to 85 C? The datasheet&#39;s 15 Ohm maximum is at VIN = 5 V, 25 C only. Our budget needs VSS at or below -3.000 V at the TMUX pins so VDD - VSS stays at or above 8 V with VDD at its 5.000 V minimum; the LDO feeding the inverter guarantees 3.2505 V minimum, leaving 250.5 mV for the inverter&#39;s loss and ripple at a load in the microamp to low-milliamp range. If no bound exists, please say so and we will measure it. If the drain must stay within VFP + 0.7 V at all times, we would appreciate TI&#39;s recommended approach: for example a Schottky from Dx to VDD, keeping VDD ungated and gating something else, or a different part in the family that specifies the drain side when unpowered. Thank you, JiahuiTPS3840LM27761TPS60403TMUX7462Ftps62120ADS131M08Broadband fixed line accessTPS22918https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1693610/hd3ss3220-hd3ss3220-usb-3-0-works-in-only-one-type-c-orientation-dir-remains-high-in-both-orientations/6528059Mon, 02 Nov 2026 20:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6faa812a-1a43-454f-9c0d-8a71f09a82a4Katy WestHi David, I understand your main concern - my questions are to help get to the root of the issue here. It is clear that the CC1/CC2 pin voltages are incorrect and because of this, ID pin is not being pulled low, so VBUS cannot work properly. Looking at just the schematic again, the only potential issue I am seeing is that the AC coupling capacitors - they are out of our recommended range of 75nF to 200 nF. Please replace them with appropriately sized capacitors and let me know if that fixes the issue. If the issue persists, please monitor the voltage on the ID pin and let me know what you see in each circumstance. I2C mode settings should not affect the ability of the MUX to control/ recognize the proper orientation. Best, Katy