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  • TI Thinks Resolved

TS5A4624: The voltage is leaked from V+ to COM

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Replies: 4

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Part Number: TS5A4624

Hi,

We got a question from the customer about TS5A4624.
Could you help us?

[Question]
When the voltage is not applied on V+ and the voltage such as 3.2V exists on NO pin, is there any possibility the voltage appears on V+? Now the voltage appears on thier own board in this condition. We know this conditon is over absolute maximum rating. But they want to know whether the voltage is leaked from NO to V+ or not.

Best Regards,
tateo

  • There are ESD protection diodes from the analog pins to V+, so the voltage will appear on V+, and the chip is likely to be powered up.
  • In reply to Clemens Ladisch:

    Tateo,

    Why do you have V+ = 0V and 3.2 V on the signal path?  What is connected to the switch?

    Also here is a diagram of what is going on in the IC.

    Thank you,

    Adam

  • In reply to Adam Torma:

    Hi, Adam-san

    Thank you for your support. This phenomenon was occurred due to design error. They will improve the schematics in next proto type.
    By the way, I have a question. I checked the datasheet of TS5A4624. I found Ino(poweroff) at Vcc=0V. So does the IC have powered-off protection?(the voltage is not leaked from NO to V+?)

    Best Regards,
    tateo

  • In reply to tateo yamashiro:

    Tateo,

    You are correct the datasheet has a leakage spec when V+ =0V.  When I place this IC on the bench and apply a voltage on the NO pin it does not leak to the V+ pin when V+ = 0V.  I have confirmed the leakage spec in the datasheet to be valid.

    I don't think the voltage on the V+ pin is coming from the NO pin.  Do you have any schematics or scope captures to what you are seeing?

    Thank you,

    Adam

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