Hi team,
My customer use the TS3USB30 in server to transmit the PCIE 100M clock and show the abnormal propagation delay and the output voltage.
Below is the schematic
Below is signal capture of the SEL and the input signal and output signal.
In above the purple one is the SEL signal, the blue one is the output signal.
In above picture, the purple one is the SEL signal, and the blue one is the input signal.
So please help to answer below question:
1. When the SEL become high, there is about 500ms delay when the output has the clock? What may be the cause for the long time delay?
2. The voltage of the input signal is 796mV, but when the output is enable, the voltage change from 796mV to 424mV. Does it make sense?
Please help to provide your comment for this issue? What may be the factor and the next step for debug?
Lacey
Thanks a lot!