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TS3DDR4000 IBIS model/s-parameters
Part Number: TS3DDR4000
I have simulated the S-parameters model you sent me a few months ago, and found the propagation delay to be about 160ps.
The spec states that the typical prop delay is 85ps.
1) What's the source of the difference?
2) What will happen with a few identical such devices on the same board? What skew can I expect between them?
Also, can you send me the model again?
I've lost the link to the source of the model I have, and I want to be sure I use the correct model
Thank you for using E2E.
The S parameter model was taken from a measurement on a PCB. The propagation delay from the model is higher due to the parasitic characteristics of the board. The specification on the datasheet for propagation delay of the device should be used for reference.
The propagation delay skew between channels is a specification provided in the datasheet as tSKEW.
The link to the model can be found in this E2E post in David's response.
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In reply to Kate Dickson:
Just checking in that your question was answered. I am marking the case resolved, but please don't hesitate to post a reply if you have any more questions!
Sorry for the late response, but I was on my weekend when you answered me.
To your response:
Since the purpose of the model is to use it in simulations, knowing the true propagation delay doesn't help me, especially in DIMM simulations, where it should give me the true propagation delay, otherwise I might get un-true skews (e.g., between Address/clock and dq/dqs)
For what load has the skew parameter in the data-sheet been defined? And what was the parasitic load in the board yielding the excess delay I see in simulations? If I know both I might be able to take advantage of Ibis VREF/CREF/RREF parameters to de-embed the extra-delay.
I know the skew spec, but I wanted to be sure it's applicable to several devices and not just between several outputs of the same device
I've looked at the model in the link you sent me, and it contains 2-port models, while what I have are 4-port models. The 4-port models are better (in my opinion), since they enable me to simulate diff pairs as well, don't you think so?
The 4-port model(s) were available once in the E2E support from November 2nd, 2015, but the link was broken, so you sent it to me, but I can't find the original now. Can you kindly send it again?
And is there any difference if I use the 2-port or the 4-port model?
In reply to Itzhak Hirshtal:
Thank you for the additional information.
The HSPICE model is available for this device on TI.com and the 2-port S-parameter model is available on E2E, linked earlier on this thread.
I am currently looking into a 4-port S-parameter model and I will get back to you within a day or two.
Thank you for your patience.
I have attached the 4-port model. Please try this one and see if you are still getting an unexpected propagation delay.
The skew parameter was calculated from the S-parameter model, so there is no external load, just the 50 ohm termination from the VNA.
For a characteristic such as propagation delay, variation from device to device may differ on the order of +/- 20% of the typical value.
I will check the 4-port model, but strangely it is not the same as the models I received a few months ago.
The models I received from you then was called Model.7z, and included models with names like DDR4_A0_B0_A1_B1_ON_25_2p5_Unit1.s4p, and similar names (4 models overall).
I would like to send it to you, but I don't see how I can upload files to your site.
I do not have the models from E2E that you are referring to. Why is it important that you must use that model?
The model I sent you came from the current design manager, so my recommendation is to use the model I sent you.
I've simulated now the new model you sent me, and it still exhibits approximately 155ps delay (measured at the 50% of the voltage swings), when connected to a DDR device DQ input with ODT=50ohm.
You wrote to me on Nov 6th: The skew parameter was calculated from the S-parameter model, so there is no external load, just the 50 ohm termination from the VNA
So, I changed the load to a pullup of 50ohms (instead of the DDR device) and now the delay is just ~100ps.
I don't know the source of the difference between the 2 simulations, but anyway it seems this model also presents a delay which isn't compatible to the data-sheet number
The model is just a guideline for device performance and may not match the actual silicon typical propagation delay. This measurement is expected for this model, based on our internal simulations.
The datasheet should be used as the reference for the typical propagation delay of the device.
I haven't heard back from you in a few days. I will go ahead and close out this thread, but feel free to reply if you have any more questions!
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