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Part Number: TS3V340
When we set D(0V) connect to S1 and S2 is floating, we could measure a 0.3C~1V on S2 pin.
Could you help to explain why S2 is not 0V?
As shown in this App Note floating pins can have all sorts of implications. What is the VCC level and are all other signals disconnected? If not, what are their signal levels and frequencies?
Thank you and best regards,
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In reply to Ambroise Suter:
D: LVDS signal.
S1: DC level = 0V with external DC cap blocking.
In reply to Patrick Chen(TPE System & Application):
depending on the frequency and voltage level the LVDS signal is running at, it could contribute up to 0.26V (500MHz, 3.3V) due to off-isolation (Figure 3 in the Datasheet).Other sources could come from parasitics within the CMOS switch.
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