• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 17 subscribers
  • Views 1133 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TS3A227E: Vdd rise and fall times

Ryuji
Guru 20090 points
Part Number: TS3A227E

Hello,

Could you please let me know the minimum and maximum Vdd rise and fall times?

In the datasheet P.47 Power supply recommendations section , there is the description that " To ensure a POR trip during a power-down and power-on event the power supply should follow the minimum and maximum V DD rise and fall times specified in the electrical specifications section."

However, I couldn't found the minimum and maximum Vdd rise and fall times from the datasheet.

Best Regards,
Ryuji

  • 0
    TI__Mastermind 45340 points

    Ryuji,

    Thank you for pointing out that we forgot to include the POR spec in the table referenced in the power supply recommendation.  I have put in a request to our design team to verify the spec so we can add it to the datasheet.

    Thank you,

    Adam

  • 0 in reply to Adam Torma
    Guru 20090 points
    Adam san,

    Thank you for your reply. Please let me know the PoR spec when the team verified the spec.

    Best Regards,
    Ryuji
  • 0 in reply to Ryuji
    TI__Mastermind 45340 points
    Ryuji,

    You have caught an error in our TS3A227E datasheet. We did not intend to mention a POR requirement in the datasheet and are going to remove that statement in the power supply recommendations section.

    Our design team says if your ramp rate is > 4.5 V/ms you will not run into POR issues due to power supply ramp rates.

    I'm sorry for the error.

    Thank you,
    Adam