Code Composer Studio forum - Recent Threads

CODECOMPOSER: J-Link (Segger) + AM263P4_ZCZ_F: CCS/UniFlash Flash Failures and Device Detection Issues

Junsin Park — Thu, 09 Apr 2026 06:45:33 GMT

Part Number: CODECOMPOSER
Other Parts Discussed in Thread: AM263P4, UNIFLASH

I am attempting to flash an image using the Segger J-Link debugger on a custom board based on the AM263P4_ZCZ_F MCU.
However, flashing has failed in both Code Composer Studio (CCS) and TI UniFlash.
I have a few questions regarding this setup.

< Development Environment >
Board: AM263P4_ZCZ_F (with on-chip 8MB flash) – custom board
TI CCS Version: 20.5.0.28__1.11.0
TI UniFlash Version: 9.5.0.5651
Debugger: Segger J-Link ULTRA+ V4.00 (J-Link/J-Flash SW V9.32)

< Questions >

Is it possible to flash using the “CCS → Run → Flash Project” menu when using a Segger J-Link debugger?
Debugging works normally, but flashing via “Flash Project” does not work.
Is it possible to flash using J-Link in TI UniFlash?
TI UniFlash also fails to flash.
Due to company security policy, I cannot attach the log file; instead, I am attaching a screenshot.
If there are any reference resources or user guides available for the AM263P4_ZCZ_F + Segger J-Link environment, I would appreciate it if you could share them.
When debugging in CCS or attempting to flash in UniFlash, the J-Link debugger does not detect the device, so I always have to manually select it (AM263P4_R5_0).

Is it possible to resolve this issue through CCS or UniFlash settings? Or should I contact Segger for support?
- When debugging in CCS: a popup appears stating that it cannot find “AM263PX.”
- When flashing in UniFlash: a popup appears stating that it cannot find “AM263PX_ZCZ_F.”

RM57L843: Unable to download Hercules lwIP example (RM57L843) from TI cgit repository

Martin Valencia — Wed, 08 Apr 2026 17:31:50 GMT

Part Number: RM57L843

Dear TI Support Team,

I am currently working with the RM57L843 Hercules microcontroller and need to access the lwIP example project available in the Hercules Examples repository.

I have attempted multiple methods to access and download the repository from official TI sources, but without success.

Repository links used:

* https://git.ti.com/cgit/hercules_examples/hercules_examples/
* https://git.ti.com/cgit/hercules_examples/hercules_examples/tree/Application/LwIP
* https://git.ti.com/cgit/hercules_examples/hercules_examples/tree/Application/LwIP/v00.04.00

Attempted download methods:

* Browser access via cgit interface (no visible or functional snapshot option)
* Direct snapshot download attempts:

* https://git.ti.com/cgit/hercules_examples/hercules_examples/snapshot/hercules_examples-master.zip
* https://git.ti.com/cgit/hercules_examples/hercules_examples/snapshot/hercules_examples-master.tar.gz
* Git clone attempts:

* git clone https://git.ti.com/hercules_examples/hercules_examples.git → HTTP 403 error
* git clone git://git.ti.com/hercules_examples/hercules_examples.git → blocked or not accessible

Observed issues:

* “Unsupported snapshot format” when attempting direct downloads
* HTTP 403 error when cloning via HTTPS
* No working download option in the cgit interface

Due to these issues, I am unable to obtain the lwIP example located under:
Application/LwIP/v00.04.00/RM57x

Could you please provide:

1. A direct and functional download link (ZIP or other format) for the Hercules Examples package, specifically including the lwIP example for RM57
2. Alternatively, a recommended official method to access or download these examples

This example is critical for implementing TCP/IP communication on the RM57 platform for an industrial data acquisition application.

Thank you for your support.

Best regards,
Martin Valencia
Senior Industrial Applications Engineer

CODECOMPOSER: Code Composer 12.4 Group Installed Application Fails to Launch

Logan Stuchlik — Wed, 08 Apr 2026 12:53:01 GMT

Part Number: CODECOMPOSER

When attempting to install Code Composer 12.4, the installation goes through with no issue.
The default configuration installs to C:/ti and all users can access and open the application.
When users open the application, on the first-time run they are prompted to select a workstation which will be shared across users.
Once that location is selected, the application fails to launch, citing a configuration issue.
It might have something to do with the eclipse/java installation that occurs during CCS installation.
Please advise what configuration is needed to allow a shared installation for users.

TMS320F2809: XDAIS v1.0.0 not able to install

Tejal Gaikwad — Wed, 08 Apr 2026 09:03:55 GMT

Part Number: TMS320F2809

I am trying to install XDAIS in CCS new version i.e. 12.8.1. getting following error
Product XDAIS v1.0.0 is not currently installed and no compatible version is available. Please install this product or a compatible version.

How to resolve this or what alll are steps to install this and which version need to install?

LAUNCHXL-F280049C: CSS scripting doesnt work on CCS 20.4.1

Surendra Nadkarni — Tue, 07 Apr 2026 13:08:58 GMT

Part Number: LAUNCHXL-F280049C

I am trying to create a debug enviornment using scripting as specified in https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_debug-scripting.html

I always endup getting following issue.

PS C:\ti\ccs2041\ccs\scripting> .\run.bat "C:\Users\surendra.nadkarni\workspace_ccstheia\sci_ex3_interrupts_fifo\read_memory.js"
[
  'Texas Instruments XDS110 USB Debug Probe_0/C28xx_CPU1',
  'Texas Instruments XDS110 USB Debug Probe_0/CLA1_0'
]
GEL: C28xx_CPU1: GEL Output:
Memory Map Initialization Complete

GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...

GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...

Target connected. Loading program...
GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...

GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...

GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...

GEL: C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...

C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:196
            throw new TimeoutError();
                  ^

ScriptingTimeoutError: Scripting operation timed out
    at waitForMessage (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:196:19)
    at Object.waitFor (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:204:17)
    at Object.receive (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:345:36)
    at receiveForModule (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:439:25)
    at receiveResponse (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:446:20)
    at execCommand (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:490:23)
    at Object.loadProgram (C:\ti\ccs2041\ccs\scripting\node_modules\scripting\syncAgent.js:557:48)
    at Object.<anonymous> (C:\Users\surendra.nadkarni\workspace_ccstheia\sci_ex3_interrupts_fifo\read_memory.js:12:16)
    at Module._compile (node:internal/modules/cjs/loader:1254:14)
    at Module._extensions..js (node:internal/modules/cjs/loader:1308:10)

Node.js v18.16.0

I am wondering what is the cause of this issue. Note that I can debug/flash the out file using CCS app. Please find the attached script file.

const ds = initScripting();

let { cores, nonDebugCores } = ds.configure("C:\\Users\\surendra.nadkarni\\workspace_ccstheia\\sci_ex3_interrupts_fifo\\targetConfigs\\TMS320F280049C_LaunchPad.ccxml");

// Configure a 10 second timeout on all operations (by default there is no timeout)
ds.setScriptingTimeout(10000);
console.log(cores);

const session = ds.openSession('Texas Instruments XDS110 USB Debug Probe_0/C28xx_CPU1');
session.target.connect();
console.log("Target connected. Loading program...");
session.memory.loadProgram("C:\\Users\\surendra.nadkarni\\workspace_ccstheia\\sci_ex3_interrupts_fifo\\CPU1_FLASH\\sci_ex3_interrupts_fifo.out");

console.log("Program loaded. Running target...");
session.target.run();
console.log("Target is running. Waiting for 5 seconds...");
sleep(5000); // Wait for the target to run for a bit before reading memory
console.log("Target is running. Reading memory...");
const symbolAddr = 0x0000a94a;
console.log(`Symbol address: ${symbolAddr}`);


// Example: Read 16 bytes from address 0x00000000
const address = symbolAddr;
const dslocation = address.toString(16) + "@DATA";
const length = 255;
const data = session.memory.read(dslocation, length, 16);
for (let i = 0; i < data.length; i++) {
    console.log(`0x${(address + i).toString(16)}: 0x${data[i].toString(16).padStart(2, '0')}`);
}
console.log(`Data read from 0x${address.toString(16)}:`, data);
session.target.disconnect()
ds.shutdown();

CCXML file

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
            <instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510c28x.xml" id="drivers" xml="tixds510c28x.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510cla2.xml" id="drivers" xml="tixds510cla2.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510cs_child.xml" id="drivers" xml="tixds510cs_child.xml" xmlpath="drivers"/>
            <property Type="choicelist" Value="4" id="SWD Mode Settings"/>
            <platform XML_version="1.2" id="platform_0">
                <instance XML_version="1.2" desc="TMS320F280049C_0" href="devices/f280049c.xml" id="TMS320F280049C_0" xml="f280049c.xml" xmlpath="devices"/>
            </platform>
        </connection>
    </configuration>
</configurations>

Second question, is there a possibility to run a GDB server using CCS tools?

Surendra

AM261X-MCAL-SDK: Debugger connection failure

Chaehee Won — Mon, 06 Apr 2026 15:48:38 GMT

Part Number: AM261X-MCAL-SDK

Hi,

I am trying to debug example project on the AM261x LP hardware. When I start debug project, I got below error. I tried to power-cycle the board as suggested but I still got same errors. I also tried to set lower TCLK (100kHz) but I still got same errors. Please help how I can fix this problem.

CS_DAP_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.4.0.3835)

LP-MSPM0L1306: SysConfig version support

Michael Steele — Mon, 06 Apr 2026 11:58:13 GMT

Part Number: LP-MSPM0L1306
Other Parts Discussed in Thread: SYSCONFIG

MSMM0 SDK Version 2.10.00.04 requires version 1.26.0 of SysConfig - the latest 1.27.0 version of SysConfig has been installed - and the project search path has been updated to locate this version however the following dialog continues to appear when attempting to open the project .syscfg file

This should fix the assosiation - however the above error persists:

MSP430F6779A: MSP430F6779A does not support usci_a_uart.c file

Sheetal kasar — Sat, 04 Apr 2026 06:59:22 GMT

Part Number: MSP430F6779A
Other Parts Discussed in Thread: MSP430WARE

I am working with the MSP430F6779A and trying to implement UART communication using DriverLib.

However, I am facing an issue where the functions in usci_a_uart.c are not getting compiled, and I receive errors indicating that UART-related macros and functions (e.g., USCI_A_UART_NO_PARITY) are undefined.

Upon investigation, I found that the condition:

#ifdef __MSP430_HAS_USCI_Ax__

used inside DriverLib is not satisfied, as this macro is not defined in the device header file (msp430f6779a.h).

Instead, I observe that macros such as:

__MSP430_HAS_EUSCI_A0__

are defined in the header file.

This leads to confusion regarding the UART peripheral type and DriverLib compatibility.

I would like clarification on the following points:

How should UART be correctly implemented on MSP430F6779A using DriverLib?
Does MSP430F6779A support standard USCI UART, or only eUSCI (enhanced UART)?
Is there a recommended or compatible version of DriverLib for this device?
Why does the device header define eUSCI-related macros while DriverLib expects USCI-related macros?
Are there any official DriverLib examples for UART on MSP430F6779A, or is register-level programming the recommended approach?

Currently, UART communication works correctly when implemented using register-level programming, as shown in the available example codes.

Kindly provide guidance on the correct approach and any recommended resources.

Thank you.

MSP430-FLASHER: Code composer issue with MSp430G2553

Luigi Quaglia — Thu, 02 Apr 2026 13:39:29 GMT

Part Number: MSP430-FLASHER
Other Parts Discussed in Thread: CCSTUDIO, MSP430G2553, MSP430FR2476

Hi,

Following the suggestion from my previous request, I have downloaded and installed the latest version of Code Composer Studio. Here are the version details:

Version: 20.5.0.28__1.11.0
Default VS Code API: 1.102.3
Extensions: Includes @ccs/ccstudio 20.5.0, @theia/ai-anthropic, and others (full list provided below).

Using this version (as well as previous ones) with the MSP430G2553, I am experiencing an issue during the debug phase: whenever the processor hits a breakpoint, it resets. To prevent this, I am currently forced to disable the Watchdog Timer (WDT) during emulation. This is very inconvenient and prevents me from performing a comprehensive debug of the application.

I previously used the Eclipse-based Code Composer Studio (up to version 10) without any issues. I have also used this device for many years with IAR Embedded Workbench and never encountered this problem; it has only started appearing with the recent versions of CCS.

Please note that my program is developed entirely in Assembly. I have also experienced the same issue with the MSP430FR2476.

I am attaching the debug configuration file from my current CCS setup. Is there a specific setting I can use to prevent the Watchdog from resetting the device during a breakpoint without having to manually disable it in the code?

Best Regards

Luigi

MSPM0G3519: CCS 20.5 compiling and linking paths broken despite being shown correctly in "explorer"

Ken Ayre — Wed, 01 Apr 2026 19:54:25 GMT

Part Number: MSPM0G3519
Other Parts Discussed in Thread: MSPM0G3507, SYSCONFIG

We recently migrated from MSPM0G3507 to G3519 and can not rebuild project in entirety.

The Include paths for compile (and linker) are not found despite being configured in project/properties, and the "reportedly missing" file still visible in the left explorer window.

**Note: some header files should not even be referenced, but ccs is still attempting to load.

I am still looking for extraneous characters that may be in some header file, but the engineering VP has added some pressure that it may be something internal to CCS or related metadata

AM6442: AM64x EVM – Error loading .out file to R5F0_0 with UniFlash

Ravilla Dinesh — Wed, 01 Apr 2026 11:06:33 GMT

Part Number: AM6442
Other Parts Discussed in Thread: UNIFLASH,

Hi Team,

Why AM64x Doesn’t Show in UniFlash GUI?

I am working with the AM6442 EVM and need guidance on flashing my application to the R5F0_0 core.

Environment:

AM6442 EVM

MCU+ SDK 10.01.00.32

CCS 12.8

Boot mode: Dev boot mode

What is the correct procedure to flash an application to the R5F0_0 core on AM64x?

Thanks & Regards,
Ravilla Dinesh.

TMS570LC4357: Query on Converting HET Pin to SCI Functionality

Prasanna Naik — Wed, 01 Apr 2026 03:48:13 GMT

Part Number: TMS570LC4357

I would like to know whether it is possible to configure an assigned HET pin to function as an SCI (UART) port.

If this is feasible, could you please share any example code or relevant user manual/documentation explaining how to perform this configuration?

XDS110ISO-EVM: IcePick_C_0: Error connecting to the target: (Error -2131 @ 0x0) Unable to access device register.

Arun N — Tue, 31 Mar 2026 23:11:53 GMT

Part Number: XDS110ISO-EVM

Hello all,

I am using the latest CCS versions on Windows 11:

Version: 20.2.0.12__1.8.0

Default VS Code API: 1.96.0

And I have encountered an issue here which pops up some times, since last few weeks, while debugging.

Is it a specific driver related issue or is there anyone who had similar issues or knows the answer, so that I can resolve this issue?

Best,

CCSTUDIO-THEIA: PROJECT ENVIRONMENT SETTING FOR MULTI CORE

Prabha mathan — Tue, 31 Mar 2026 13:49:33 GMT

Part Number: CCSTUDIO-THEIA

I am trying to set a project environment for multicore. i am using TM320F28388D controller and it has 3 cores. in which i want to make use of all the three cores. so i need a support on how to setup the environment for multicore. is it like need to create seperate projects for all the three cores or in a single project we can setup the environment for multicore. during new project setup i noticed in the project wizard page in the project file space i can see few options which says Driverlib Empty CM Example CCS Project and Driverlib Empty CPU1 Example CCS Project we have to follow these things to setup for multicore thing.

AM6442: Is syscfg_c.rov.xs used when debugging PRU cores?

Nick Saulnier — Tue, 31 Mar 2026 13:23:27 GMT

Part Number: AM6442

My understanding of this file is that it is helpful for debugging RTOS projects, but not actually used for debugging PRU cores (which are bare metal projects). Is that correct?

If so, I will remove this file from all the PRU firmware projects in the OpenPRU repo:
https://github.com/TexasInstruments/open-pru/pull/129

syscfg_c.rov.xs

/*
 *  ======== syscfg_c.rov.xs ========
 *  This file contains the information needed by the Runtime Object
 *  View (ROV) tool.
 */
var crovFiles = [
    "kernel/freertos/rov/FreeRTOS.rov.js",
];

Question #2, is this file still used by NORTOS MCU+ SDK cores? Or since NORTOS does not use FreeRTOS, does that mean that this file is unused for the NORTOS projects as well?

Question #3, should I update the syscfg_c.rov.xs file for all my MCU+ cores to add FreeRTOS_Theia? This won't break backwards compatibility with older versions of CCS and MCU+ SDK, right?

/*
 *  ======== syscfg_c.rov.xs ========
 *  This file contains the information needed by the Runtime Object
 *  View (ROV) tool.
 */
var crovFiles = [
    "kernel/freertos/rov/FreeRTOS.rov.js",
];

var objectViewerFiles = [
    "kernel/freertos/rov_theia/FreeRTOS_Theia.rov.js",
];

Thanks,

Nick

MSPM0G3507: ADC Conversion Not Synchronizing with PWM (MSPM0G3507)

Sakthivel Pavadai — Tue, 31 Mar 2026 04:51:45 GMT

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

I am working on the MSPM0G3507 MCU and trying to synchronize ADC conversion with a PWM signal.

My requirement is as follows:

PWM frequency: 100 kHz
I need to sample 10 ADC values within one PWM cycle
This means I need 1 ADC conversion every 1 µs
All samples must be synchronized to the PWM cycle (same phase every cycle)

What I have tried:

Configured PWM as event publisher
Configured Timer as subscriber to PWM
Configured Timer as publisher
Configured ADC as subscriber to Timer

So the chain is:

PWM → Timer → ADC

Issues:

ADC conversions are not properly synchronized with PWM
- Samples are drifting across multiple PWM cycles, or
- Not restarting correctly on every PWM edge
- I am not getting consistent 10 samples within a single PWM period
I am also unable to set PWM duty cycle to exactly 50% at 100 kHz frequency

Expectation:

On every PWM edge:
- Timer should start/reset
- ADC should take exactly 10 samples at 1 µs intervals
- Sampling should repeat identically every PWM cycle

Questions:

What is the correct configuration to achieve this synchronization?
Why might PWM duty cycle not be achieving an exact 50% at 100 kHz?

Any example configuration or reference project would be very helpful.

Thanks in advance!

Best regards,

SAKTHIVEL P

Director- Semiconductors & Sensors

Rotary Electronics Pvt. Ltd.

# 18, 5th cross, 4th stage, 4th main, Industrial Town,

Rajajinagar, Bangalore - 560 044, India

LAUNCHXL2-570LC43: SafeTI Library Expected Results

Christopher Federici — Mon, 30 Mar 2026 22:55:59 GMT

Part Number: LAUNCHXL2-570LC43
Other Parts Discussed in Thread: TMS570LC4357

Hello

I have opened the SafeTI Diagnostic Library v2.4.0 demo_app and updated per the two forum posts below:

After doing this, following files are generated to debug folder:

1. 1. ..\SL_TMS570LC4357_NoOS\Debug\Profile_tests.txt
  2. ..\SL_TMS570LC4357_NoOS\Debug\Profile_pbist_tests.txt

I have the following questions about this:

Are there expected failures in this demo? periodicSTFailCount is set to 10 at end.
If I put a breakpoint at first call to _c_int00 within resetEntry function, it will not hit on the first execution - instead the program will stop at entry to main and I can run it from there. However, if I use CCS menu (Run->Reset->CPU Reset) then the PC starts at this line / breakpoint. How come it isn't hit without doing the soft reset?
If I check the result file Profile_pbist_tests.txt, it seems incomplete. THe last two lines are :

PBIST_RAMGROUP_30_L2RAMW PBIST_RAMGROUP_05_AWM1 0 0 0 0
PBIST_RAMG

Is this expected?
If I check Profile_tests.txt it seems not all tests are executed. Following tests show execution count equal to 0. Are more changes required to run all these tests?
PBIST_EXECUTE
PBIST_EXECUTE_OVERRIDE
EFUSE_SELF_TEST_AUTOLOAD
STC1_RUN
STC1_COMPARE_SELFCHECK
STC2_RUN
STC2_COMPARE_SELFCHECK
PSCON_PMA_TEST
MEMINTRCNT_SELFTEST
PERIPHSEGINTRCNT_UNPRIVELEGED_ACCESS
ADC_SELFTEST_ALL

Thank you in advance for the support and examples. I have attached the output of my tests below:

Profile_pbist_tests.txt

Profile_tests.txt

F29H859TU-Q1: How to use the "Cybershield lit Tool"

HIROKI YAMAGUCHI — Mon, 30 Mar 2026 10:45:06 GMT

Part Number: F29H859TU-Q1
Other Parts Discussed in Thread: CSD

The “F29H85x Keys Provisioning” process fails.
What do you think could be the cause?

We have attached screenshots of the tool and the log files.

Also, is there a user guide or documentation for the Cybershield Kit Tool?

■Screen capture

■Log

Starting TI Cybershield Toolkit Wizard...
Device changed to: F29H85X
Setting up F29 development session with data: {'smpk_algo': 'rsa4k', 'bmpk_algo': 'rsa4k', 'type': 'f29_development'}
Generate F29 certificate: {'device': 'f29h85x', 'msv': '0x1E22D', 'flags': ['msv_protect', 's_protect', 'smek_protect', 'b_protect', 'bmek_protect', 'keycnt_protect', 'smpk', 'smek', 'bmpk', 'bmek'], 'output_dir_path': 'C:\\Users\\hiroki_yamaguchi\\ti\\f29h85x\\certificates', 'pub_key_path': 'C:/ti/otp_keywriter_f29h85x_SR_10_1_01_00/sbl_keywriter/scripts/cert_gen/common/tifek/f29h85x/SR_10/ti_fek_public.pem', 'dev_sr_ver': 'SR_10', 'keycnt': '2', 'keyrev': '1', 'sr_sbl': '1', 'sr_hsmRT': '1', 'sr_app': '1', 'sr_ssu': '1', 'ext_otp': '0x80000001', 'ext_otp_indx': '0', 'ext_otp_size': '32', 'smpk_signing_algorithm': 'rsa4k', 'bmpk_signing_algorithm': 'rsa4k'}
Generating certificate with data: {'device': 'f29h85x', 'msv': '0x1E22D', 'flags': ['msv_protect', 's_protect', 'smek_protect', 'b_protect', 'bmek_protect', 'keycnt_protect', 'smpk', 'smek', 'bmpk', 'bmek'], 'output_dir_path': 'C:\\Users\\hiroki_yamaguchi\\ti\\f29h85x\\certificates', 'pub_key_path': 'C:/ti/otp_keywriter_f29h85x_SR_10_1_01_00/sbl_keywriter/scripts/cert_gen/common/tifek/f29h85x/SR_10/ti_fek_public.pem', 'dev_sr_ver': 'SR_10', 'keycnt': '2', 'keyrev': '1', 'sr_sbl': '1', 'sr_hsmRT': '1', 'sr_app': '1', 'sr_ssu': '1', 'ext_otp': '0x80000001', 'ext_otp_indx': '0', 'ext_otp_size': '32', 'smpk_signing_algorithm': 'rsa4k', 'bmpk_signing_algorithm': 'rsa4k'}
Using development session mode
DEBUG: F29 certificate generation command: script_name --device f29h85x --smpk_signing_algorithm rsa4k --bmpk_signing_algorithm rsa4k gencert -t C:/ti/otp_keywriter_f29h85x_SR_10_1_01_00/sbl_keywriter/scripts/cert_gen/common/tifek/f29h85x/SR_10/ti_fek_public.pem --msv 0x1E22D --msv_protect --bmpk --bmek --b_protect --bmek_protect --smpk --smek --s_protect --smek_protect --sr_sbl 1 --sr_hsmRT 1 --sr_app 1 --sr_ssu 1 --keycnt 2 --keycnt_protect --keyrev 1 -d f29h85x --devSrVer SR_10 --ext_otp 0x80000001 --ext_otp_indx 0 --ext_otp_size 32
DEBUG: Calling f29_main()
-----------------------------------------------
F29H85x CyberShiled Toolkit CLI
-----------------------------------------------
deleting the session Development
Creating Development Session
Saving Development session...
opening session: Development
# Using SWREV_SEC_APP: 0xb'\x00\x00\x00\x01'
# Using SWREV_SSU: 0xb'\x00\x00\x00\x01'
# Using SWREV_SBL: 0xb'\x00\x00\x00\x01'
# Using SWREV_HSMRT: 0xb'\x00\x00\x00\x01'
# Using MSV[6:0]: 0x123437
# Using Key Count: 0x$3
# Using Key Rev: 0x1
Generating Dual signed certificate!!
# encrypt aes256 key with tifek public part
# encrypt SMPK-priv signed aes256 key(hash) with tifek public part
# encrypt smpk-pub hash using aes256 key
# encrypt smek (sym key) using aes256 key
# encrypt ext_otp using aes256 key
# encrypt BMPK-priv signed aes256 key(hash) with tifek public part
# encrypt bmpk-pub hash using aes256 key
# encrypt bmek (sym key) using aes256 key
primary cert: signing with SigningAlgorithm.PKCS1_V15
secondary cert: signing with SigningAlgorithm.PKCS1_V15
writing certificates into C:\Users\hiroki_yamaguchi\ti\f29h85x\certificates
Certificate generated successfully
DEBUG: F29 certificate generation completed successfully
C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x
C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x\F29h85x-hsse.ccxml
Target configuration file copied to: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x\F29h85x-hsse.ccxml
Target configuration file applied: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x\F29h85x-hsse.ccxml
DEBUG: Signing specific F29H85x binaries: ['ram_based_uart_sbl.bin', 'tifs_f29h85x_hs_se_code_provisioning.release.bin']
DEBUG: F29H85x specific binary signing requested
DEBUG: Using session: Development
DEBUG: Development session with SMPK: rsa4k, BMPK: rsa4k
DEBUG: Using prebuilt images directory: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images
Signing ram_based_uart_sbl.bin...
DEBUG: Signing binary ram_based_uart_sbl.bin with parameters:
- Core: C29
- Boot: RAM
- KeyRev: 1
- LoadAddr: 0x200E1000
- SwRv: 1
- CCS Path: C:/ti/ccs2011
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
writing signed images into C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
Signing tifs_f29h85x_hs_se_code_provisioning.release.bin...
DEBUG: Signing binary tifs_f29h85x_hs_se_code_provisioning.release.bin with parameters:
- Core: HSM
- Boot: RAM
- KeyRev: 1
- LoadAddr: 0x00000000
- SwRv: 1
- Debug: DBG_SOC_DEFAULT
- CCS Path: C:/ti/ccs2011
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
writing signed images into C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
Target configuration file copied to: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x\F29h85x-hsse.ccxml
Detecting device with boot mode: JTAG, connection info: {'type': 'jtag', 'ccs_path': 'C:/ti/ccs2011'}
Error during JTAG detection: 'F29H85xDeviceModel' object has no attribute 'run_command'
2026-03-30 16:59:02,530 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Running Get Device Type command: C:/ti/ccs2011\ccs\scripting\run.bat C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\apps\tifs\kp_cp_f29h85x\read_lifecycle.js
2026-03-30 16:59:02,533 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Using CCXML path: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\src\apps\tifs\kp_cp_f29h85x\F29h85x-hsse.ccxml
2026-03-30 16:59:11,121 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Command output:
Device is in HS_FS state

Device is in HS_FS state

2026-03-30 16:59:11,122 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Get Device Type completed successfully
DEBUG: Signing binary tifs_f29h85x_hs_se.release.bin with parameters:
- Core: HSM
- Boot: FLASH
- KeyRev: 1
- LoadAddr: 0x00000000
- SwRv: 1
- Debug: DBG_SOC_DEFAULT
- CCS Path: C:/ti/ccs2011
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
writing signed images into C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
DEBUG: Signing binary csd.bin with parameters:
- Core: C29
- Boot: FLASH
- KeyRev: 1
- LoadAddr: 0x10001000
- SwRv: 1
- CCS Path: C:/ti/ccs2011
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
writing signed images into C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
DEBUG: Signing Sec-Cfg default_seccfg_bankmode_0_ssumode1.out with parameters:
- KeyRev: 1
- SwRv: 1
- Boot: FLASH
- CCS Path: C:/ti/ccs2011
Using CCS path: C:\ti\ccs2011
Created temporary directory: C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71
Processing on Windows platform - CCS path: C:/ti/ccs2011
Found c29objcopy tool at: C:\ti\ccs2011\ccs\tools\compiler\ti-cgt-c29_2.0.0.STS\bin\c29objcopy.exe
Preparing commands for extracting CPU configurations...
Extracting CPU1 configuration...
Executing: Extracting CPU1 configuration
Command: "C:\ti\ccs2011\ccs\tools\compiler\ti-cgt-c29_2.0.0.STS\bin\c29objcopy.exe" -O binary --only-section=.TI.bound:CPU1_Cfg "C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\default_seccfg_bankmode_0_ssumode1.out" "C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu1.bin"
SUCCESS: Extracting CPU1 configuration completed successfully
Extracting CPU2 configuration...
Executing: Extracting CPU2 configuration
Command: "C:\ti\ccs2011\ccs\tools\compiler\ti-cgt-c29_2.0.0.STS\bin\c29objcopy.exe" -O binary --only-section=.TI.bound:CPU2_Cfg "C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\default_seccfg_bankmode_0_ssumode1.out" "C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu2.bin"
SUCCESS: Extracting CPU2 configuration completed successfully
Extracting CPU3 configuration...
Executing: Extracting CPU3 configuration
Command: "C:\ti\ccs2011\ccs\tools\compiler\ti-cgt-c29_2.0.0.STS\bin\c29objcopy.exe" -O binary --only-section=.TI.bound:CPU3_Cfg "C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\default_seccfg_bankmode_0_ssumode1.out" "C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu3.bin"
SUCCESS: Extracting CPU3 configuration completed successfully
Checking for CPU configuration files in C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71
Found CPU1 configuration file: C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu1.bin (size: 2048 bytes)
Found CPU2 configuration file: C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu2.bin (size: 2048 bytes)
Found CPU3 configuration file: C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu3.bin (size: 2048 bytes)
Truncating CPU2 configuration file: C:\Users\HIROKI~1\AppData\Local\Temp\tmpqa4qjj71\seccfgCpu2.bin
Successfully truncated seccfgCpu2.bin from 2048 to 2032 bytes
CPU configuration file preparation completed successfully
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
writing certificates into C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
Creating output directory: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
Successfully created or verified output directory: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
opening session: Development
primary cert: signing with SigningAlgorithm.PKCS1_V15
Creating combined output file: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages\seccfg.bin
Successfully wrote combined SecCfg to: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages\seccfg.bin
Using signed UART kernel: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages\ram_based_uart_sbl.cert.bin
Using signed HSM CP image: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages\tifs_f29h85x_hs_se_code_provisioning.release.hs.hsmimage
Using signed JTAG HSM CP image: C:\Users\hiroki_yamaguchi\ti\f29h85x\signedImages\tifs_f29h85x_hs_se_code_provisioning.release.hs.hsmimage
2026-03-30 17:00:34,690 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Running key provisioning with command: C:/ti/ccs2011\ccs\scripting\run.bat C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\apps\tifs\kp_cp_f29h85x\run_keyprov_flow.js --otp-kw-bin C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\otp_kw_f29h85x_hs_fs.hsmimage.bin --certificate C:\Users\hiroki_yamaguchi\ti\f29h85x\certificates\final_certificate.bin --jtag-kernel C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\secure_ram_based_jtag_kernel.out
2026-03-30 17:00:44,689 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Command output:
Loading OTP KW binary from: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\otp_kw_f29h85x_hs_fs.hsmimage.bin
Loading certificate from: C:\Users\hiroki_yamaguchi\ti\f29h85x\certificates\final_certificate.bin
Loading JTAG flash kernel from: C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\host\bin\f29x_prebuilt_images\secure_ram_based_jtag_kernel.out
Expecting target to not halt for 10 seconds
Log file contents:

2026-03-30 17:00:44,689 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - WARNING - Command errors:
Failure: Halted unexpectedly after removing both breakpoints.

2026-03-30 17:00:44,690 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Key provisioning completed successfully
2026-03-30 17:00:44,693 - apps.qtgui.utils.log_parser - WARNING - Could not find repository base, using current directory
2026-03-30 17:01:14,522 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Running Get Device Type command: C:/ti/ccs2011\ccs\scripting\run.bat C:\Users\HIROKI~1\AppData\Local\Temp\_MEI154122\apps\tifs\kp_cp_f29h85x\read_lifecycle.js
2026-03-30 17:01:17,524 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Command output:
Device is in HS_FS state

Device is in HS_FS state

2026-03-30 17:01:17,524 - apps.tifs.kp_cp_f29h85x.jtag_provisioning - INFO - Get Device Type completed successfully

AM2434: AM2434: Data Abort on ldrexd during 64-bit atomic write to Shared MSRAM

Eli Mordel — Sun, 29 Mar 2026 14:18:26 GMT

Part Number: AM2434

Hi,

I am working on a multicore application using the AM2434 (FreeRTOS) and am running into a hardware exception regarding atomic memory accesses.

The Architecture:

Core-1 (Server): Writes a 64-bit variable to a shared MSRAM region.
Other Cores (Clients): Constantly polling/reading this exact same 64-bit memory address.

The Memory Configuration: The shared MSRAM region is configured in the MPU with the following attributes:

Memory Type: Normal

Cache Policy: Non-Cacheable, Non-Bufferable (TEX=001, C=0, B=0)

Shareability: Shareable (S=1)

Permissions: Supervisor RW, User RW, Execute Never

The Problem: To prevent torn reads across the cores, I am using the standard ATOMIC_STORE macro for the 64-bit write. The compiler correctly generates the ldrexd and strexd instructions.

However, when stepping through the disassembly in Code Composer Studio, the CPU throws a Data Abort exception the exact moment it tries to execute the ldrexd command on this shared memory pointer.

My Questions:

1.Does the AM2434 interconnect/AXI bus support the Global Exclusive Monitor for the shared MSRAM region to allow ldrexd/strexd instructions?

2.If the Exclusive Monitor is not supported here, what is the recommended TI solution for locking shared memory or safely passing 64-bit variables between cores without torn reads?

Thanks,

Regards,

Eli

MSPM0-SDK: issues with flash burning on LP-MSPM0G3519 on OSX platform (Mac M4)

William Wiese — Sun, 29 Mar 2026 08:04:03 GMT

Part Number: MSPM0-SDK
Other Parts Discussed in Thread: LP-MSPM0G3519, MSPM0G3519

TI HW: LP-MSPM0G3519, XDS110 firmware 3.0.0.32
Host: MacBook Air M4 2025, macOS 26.1 (pre-release/beta)
Symptoms: Error -1141 from all tools (DSLite, CCS Theia, CCS Cloud, pyocd)
What works: SWD DPIDR reads correctly (0x6BA02477)
What fails: CDBGPWRUPACK never asserts — all AP accesses return FAULT ACK
Tools tried: DSLite 20.0.0.3178, DSLite 20.5.0.3900, pyOCD 0.43.1, OpenOCD master, CCS Cloud
Key observation: pyOCD verbose log shows failure at DebugPortStart sequence, WriteAP returns
FAULT ACK — the debug power domain never comes up

Root cause hypothesis: MSPM0G3519 CS-DAP requires PWRAP AP write before CDBGPWRUPACK, but standard SWD tools can't access PWRAP without CDBGPWRUPACK — requires GEL_EvalOnTarget via CS_DAP_0 which only DSLite supports, and DSLite fails due to macOS 26.1 USB timing issues

Q: "Has anyone successfully flashed LP-MSPM0G3519 from macOS, and is there a known workaround for the CDBGPWRUPACK cold-start issue without DSLite/GEL?"

Thanks.
Bill

TMS320F28377D: About the compiler documentation

Mustafa Cakmak — Fri, 27 Mar 2026 22:43:54 GMT

Part Number: TMS320F28377D

Hi, the ASM output generated after compilation does not match the output shown for the __abs16_sat function in the “Intrinsics” section of the TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User's Guide (Rev. Z). Page 163 states the following:

SETC OVM

MOV AH, src

ABS ACC

MOV dst , AH

CLRC OVM

However, when I compile it, the output is as follows:

SETC OVM ;

SETC SXM ;

MOV ACC,AL << 16 ;

ABS ACC ;

MOV AL,AH ;

CLRC OVM ;

Here, “SETC SXM” has been added, and the line “MOV AH, src” has been changed to “MOV ACC,AL << 16”. Of course, I understand this adjustment was made to ensure the function runs safely. However, I believe these changes should also be noted in the documentation. I need to provide my manager with a reference containing the actual code to use these functions. I’m not sure where else there are differences. I’d appreciate any help you can offer.

Note: I’m using CCS. The compiler version is v22.6.1.LTS. For this compiler, I’m directed to the same documentation as for version v22.6.0.LTS.

CCSTUDIO-THEIA: Integration of (external) SAST tools

Josef Luttenbacher — Fri, 27 Mar 2026 12:02:55 GMT

Part Number: CCSTUDIO-THEIA

Will external code checking tools like Parasoft C/C++ Test, QA-Systems MISRA + CANTATA, Perforce QAC, Vector PC-Lint, which all of them usually provide extenstions for Visual Studio Code, integrate with (Theia based) Code Composer Studio V20.0.x? Has integration of any of these tools already been proven so far? Does TI partner with any of these tool manufacturers for integration into CCS V20?

All of these tools do provide also Eclipse plugins, but as CCS is no more eclipse based, this does not help.

AM62A7-Q1: Unable to connect XDS560v2 to AM62a EVM

Parthkumar Patel — Thu, 26 Mar 2026 22:28:45 GMT

Part Number: AM62A7-Q1

Tool/Software: XDS560v2 STM, CCS 20.2.0, MCU+ SDK 11.01.00.06

Topic: AM62A: XDS560v2 "SC_ERR_ECOM_EMUNAME" (Error -250) and JTAG-based NAND Flashing in No Boot Mode

1. Connection Issue (Error -250): Despite the XDS560v2 being recognized in the Windows Device Manager, the CCS "Test Connection" fails immediately with the following log:

E_RPCENV_IO_ERROR(-6) No connection: DTC_IO_Open::dtc_conf The value is '-250' (0xffffff06). The title is 'SC_ERR_ECOM_EMUNAME'. Explanation: An attempt to access the debug probe via USCIF ECOM has failed.

We have verified the USB connection and tried Spectrum Digital XDS560V2 STM USB Emulator/Spectrum Digital XDS560V2 STM TRAVELER Emulator config.
power LED is green and state 3 led is red. no other LED blinks. Activity LED1 blinked green initilaly on connection.
No other JTAG hardware connected to EVM.

Question: Is there a specific "Connection Property" or "Emulator Selection" setting required for the AM62A target configuration to resolve this ECOM name error? or we are missing something here?

2. NAND Flashing via JTAG in No Boot Mode: Once the connection is resolved, our primary goal is to flash the NAND memory using JTAG while the board is in No Boot mode. How do we achieve this? Is there any documenation for this?

AM62A7-Q1: Unable to debug and verify DDR function using XDS110 and CCS

Parthkumar Patel — Thu, 26 Mar 2026 21:55:50 GMT

Part Number: AM62A7-Q1

We are working with the AM62A EVM and an XDS110 debugger. We are following the MCU+ SDK 11.01.00.06 documentation for debugging and DDR initialization testing, but we are facing two primary blockers.

Our Setup:

Hardware: AM62A7-SK EVM (PROC135A)
Debugger: XDS110 (via JTAG)
SDK: MCU+ SDK v11.01.00.06
CCS: v20.2.0
Boot Mode: No Boot Mode (as per SDK EVM Setup Page)
Status: "Test Connection" in .ccxml passes successfully.

Issue 1: DDR Initialization Failure & Core Connectivity

We are following the "Project-less" debug flow. Upon launching the target configuration, all cores appear as "Disconnected." We used default settings for target seetings like freq, GEL files, Address etc.

We can only successfully connect to the WKUP_R5FSS0_0 core.
When attempting to run Scripts --> AM62 DDR Initialization -> AM62A_DDR_Initialization_ECC_Disabled, we receive the following error:

WKUP_R5FSS0_0: Trouble Writing Memory Block at 0xf300120 on Page 0 of Length 0x4: (Error -1065 @ 0xF300124) Unable to access device memory.

Questions:

Why are the other cores (A53, R5F_0, etc.) failing to connect? Which boot mode shall be used for this?
Does the WKUP_R5F require to follow recommended sequence to verify DDR init, read/write? how?
Is there a way we can write data onto NAND using JTAG by providing start address, size and data itself? Which mode we can use for it? Is there documentation for this?

Issue 2: "No Compatible Debug Core Found" during App Debug

When attempting to build and debug a basic test application following the CCS Getting Started Guide:

The board is kept in No Boot mode.
After creating project and Upon clicking "Debug," CCS prompts to select a core, but then returns: "No compatible debug core found."

Questions:

Is "No Boot" the correct mode for loading an application binary directly via CCS/JTAG, or should we be use other Boot mode"?
Do we need to manually run the SOC Initialization script (GEL) before CCS recognizes the cores as compatible for the project? any example for it?
Can we do debugging of specific single core or multiple cores in Nand boot mode? how?

TMS320C6711D: No one here knows how to set up CCS to burn existing code into DSPs

Thomas Drewke — Thu, 26 Mar 2026 12:02:00 GMT

Part Number: TMS320C6711D

I have a legacy problem. We own a large stock of, and use, TMS320C6711Dxxx DSPs on a legacy product we still manufacture. We have finished code created years ago, and we used to burn this code into the DSPs using an old copy of CCS and a slightly-obsolete Blackhawk USB-based programming tool. All of this was on an ancient Windows 7 machine which has gone bad.

No one here in Engineering ever uses CCS for anything- the people who did are long gone. SO although I have been able to download and install a current copy of CCS on my nice new Windows 11 PC, and although I could recover files from the old hard drive, I have NO idea how to find which specific files are needed to burn our code into these DSPs. Nor do I have a clue as to how to set up a burn session on CCS if I did have the files.

I have installed and I have no problem with the Blackhawk programming hardware. It's recognized and working on Windows 11. But I need a lot of help building some kind of project which would let me burn the old code into our old DSPs.