I spent some time looking for this so I'm adding this post which might save time for others.
The memory map for the C674x is defined on pg 39 of sprs614a.pdf (TMS320DM8168, TMS320DM8167, TMS320DM8166, TMS320DM8165 SPRS614A–MARCH 2011–REVISED AUGUST 2011)
It matches the definitions in the gel file evm816x.gel which I downloaded as part of the link here:
Get the Davinci device support package from : http://processors.wiki.ti.com/index.php/Download_CCS
I downloaded from the link called “DaVinci (DMxxxx) v1.0.3”.
Here is an extract:
/* C674x Memory Map */
GEL_MapAddStr( 0x00400000, 0, 0x00040000, "R|W|AS4", 0 ); // C674x UMAP1 (HDVICP2-0 SL2)
GEL_MapAddStr( 0x00500000, 0, 0x00040000, "R|W|AS4", 0 ); // C674x UMAP1 (HDVICP2-1 SL2)
GEL_MapAddStr( 0x00800000, 0, 0x00040000, "R|W|AS4", 0 ); // C674x UMAP0 (L2 RAM)
GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 ); // C674x L1P Cache/RAM
GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 ); // C674x L1D Cache/RAM
GEL_MapAddStr( 0x01800000, 0, 0x00400000, "R|W|AS4", 0 ); // C674x Internal CFG registers
GEL_MapAddStr( 0x08000000, 0, 0x01000000, "R|W|AS4", 0 ); // L4 Standard Domain
GEL_MapAddStr( 0x09000000, 0, 0x00100000, "R|W|AS4", 0 ); // EDMA TPCC Registers
GEL_MapAddStr( 0x09800000, 0, 0x00100000, "R|W|AS4", 0 ); // EDMA TPTC0 Registers
GEL_MapAddStr( 0x09900000, 0, 0x00100000, "R|W|AS4", 0 ); // EDMA TPTC1 Registers
GEL_MapAddStr( 0x09A00000, 0, 0x00100000, "R|W|AS4", 0 ); // EDMA TPTC2 Registers
GEL_MapAddStr( 0x09B00000, 0, 0x00100000, "R|W|AS4", 0 ); // EDMA TPTC3 Registers
GEL_MapAddStr( 0x0A000000, 0, 0x01000000, "R|W|AS4", 0 ); // L4 High-Speed Domain
GEL_MapAddStr( 0x10000000, 0, 0x01000000, "R|W|AS4", 0 ); // C674x L1/L2 C674x Internal Global Address
