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CCS5, System Analyzer

Yan Tsitrin
Prodigy 240 points

Hi, folks,

Is anybody knows where can I find info regarding using Multicore System Analyzer for am335x EVM with CCS 5.1.1?

I tried to go according to their  tutorial http://processors.wiki.ti.com/index.php/Multicore_System_Analyzer, but it totally does not work with am335x.

Thank you in advance,

Yan

  • 0
    TI__Guru**** 171004 points

    Yan,

    I was able to reproduce this issue with all the System Analyzer examples for Cortex A8 and filed the bug report SDOCM00099778. You can check its status at the link SDOWP in my signature below.

    I apologize for the inconvenience,

    Rafael

  • 0 in reply to desouza
    TI__Mastermind 20805 points

    There have been a number of improvements to UIA and System Analyzer for the soon-to-be-released CCSv5.4.

    I just built and ran the UIA stairstep stop-mode JTAG app for the beaglebone and it worked fine.

    You should probably update to CCSv5.4 if you want to use UIA.

    The problem that Rafael had was related to the peripheral clocks not being enabled for the DM timers.  This was causing a memory exception (memory read/write fails if the peripheral is not enabled).  There's a .gel file workaround to enable these clocks for the beaglebone.   I am going to close SDOCM00099778 and I opened a new bug asking that we add some code to SYS/BIOS to enable the clock for the timer peripherals so that users don't have to manage this themselves (SDOCM00101061).

    #define CM_PER            (0x44e00000)
    #define CM_DPLL            (0x44e00500)

    #define CM_PER_TIMER2_CLKCTRL    (CM_PER + 0x80)
    #define CM_PER_TIMER3_CLKCTRL    (CM_PER + 0x84)
    #define CM_PER_TIMER4_CLKCTRL    (CM_PER + 0x88)
    #define CM_PER_TIMER5_CLKCTRL    (CM_PER + 0xEC)
    #define CM_PER_TIMER6_CLKCTRL    (CM_PER + 0xF0)
    #define CM_PER_TIMER7_CLKCTRL    (CM_PER + 0x7C)

    #define CLKSEL_TIMER2_CLK    (CM_DPLL + 0x04)
    #define CLKSEL_TIMER3_CLK    (CM_DPLL + 0x08)
    #define CLKSEL_TIMER4_CLK    (CM_DPLL + 0x0C)
    #define CLKSEL_TIMER5_CLK    (CM_DPLL + 0x14)
    #define CLKSEL_TIMER6_CLK    (CM_DPLL + 0x18)
    #define CLKSEL_TIMER7_CLK    (CM_DPLL + 0x00)

    hotmenu EnableTimers_32KHz()
    {
        WR_MEM_32(CM_PER_TIMER2_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER2_CLK, 0x2);

        WR_MEM_32(CM_PER_TIMER3_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER3_CLK, 0x2);

        WR_MEM_32(CM_PER_TIMER4_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER4_CLK, 0x2);

        WR_MEM_32(CM_PER_TIMER5_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER5_CLK, 0x2);

        WR_MEM_32(CM_PER_TIMER6_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER6_CLK, 0x2);

        WR_MEM_32(CM_PER_TIMER7_CLKCTRL, 0x2);
        WR_MEM_32(CLKSEL_TIMER7_CLK, 0x2);

        GEL_TextOut("Timers 2-7 enabled for 32KHz.\n");

    }

    Thanks,
    -Karl-