Hi all,
I'm debugging a new board that carry six DSP 6670 and one 6678, having had a bad experience with JTAG of multiple DSP I shared the seven DSP with three JTAG daisy chains (three 14pin connectors), with buffer/level shifter (74AVC2T45) as required by the documentation for multi DSP configuration. All the seven DSP works perfecly well but I'm not able to use the JTAG chains, seems to me very strange that also using a low speed configuration I'm not able to use the jtag.
See the attach log of my 560v2 debugger (two 6670 in chain), could some one help me?
Thanx
Maxx
[Start: Spectrum Digital XDS560V2 STM USB Emulator_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\massimo\AppData\Local\TEXASI~1\
CCS\ti\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv6\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Apr 27 2016'.
The library build time was '20:54:47'.
The library package version is '6.0.228.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv6\ccs_base\common\uscif\dtc_top.jbc
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 none - 01 00 500.0kHz - similar isit internal clock
2 none - 01 09 570.3kHz {-} similar isit internal clock
3 64 - 01 00 500.0kHz O good value measure path length
4 16 - 01 00 500.0kHz ? bad value auto step initial
5 64 - 01 00 500.0kHz ? bad value auto power initial
6 64 - 01 00 500.0kHz ? bad value auto power delta
7 64 - 02 32 445.3kHz ? bad value auto margin initial
8 64 - 02 26 398.4kHz ? bad value auto margin delta
9 64 - 02 1B 355.5kHz ? bad value auto margin delta
10 64 - 02 12 320.3kHz ? bad value auto margin delta
11 64 - 02 0A 289.1kHz ? bad value auto margin delta
12 64 - 02 02 257.8kHz i stuck ir auto margin delta
13 64 - 03 36 230.5kHz ? bad value auto margin delta
14 64 - 03 2A 207.0kHz ? bad value auto margin delta
15 64 - 03 1F 185.5kHz ? bad value auto margin delta
16 64 - 03 15 166.0kHz ? bad value auto margin delta
17 64 - 03 0C 148.4kHz ? bad value auto margin delta
18 64 - 03 04 132.8kHz ? bad value auto margin delta
19 64 - 04 3A 119.1kHz ? bad value auto margin delta
20 64 - 04 2D 106.4kHz ? bad value auto margin delta
21 64 - 04 22 95.70kHz ? bad value auto margin delta
22 64 - 04 18 85.94kHz ? bad value auto margin delta
23 64 - 04 0F 77.15kHz ? bad value auto margin delta
24 64 - 04 07 69.33kHz ? bad value auto margin delta
25 64 - 04 00 62.50kHz ? bad value auto margin delta
26 64 - 05 32 55.66kHz ? bad value auto margin delta
27 64 - 05 26 49.80kHz ? bad value auto margin delta
28 64 - 05 1B 44.43kHz ? bad value auto margin delta
29 64 - 05 12 40.04kHz ? bad value auto margin delta
30 64 - 05 0A 36.13kHz ? bad value auto margin delta
31 64 - 05 02 32.23kHz ? bad value auto margin delta
32 64 - 06 36 28.81kHz ? bad value auto margin delta
33 64 - 06 2A 25.88kHz ? bad value auto margin delta
34 64 - 06 1F 23.19kHz ? bad value auto margin delta
35 64 - 06 15 20.75kHz ? bad value auto margin delta
36 64 - 06 0C 18.55kHz ? bad value auto margin delta
37 64 - 06 04 16.60kHz ? bad value auto margin delta
38 64 - 07 3A 14.89kHz ? bad value auto margin delta
39 64 - 07 2D 13.31kHz ? bad value auto margin delta
40 64 - 07 22 11.96kHz ? bad value auto margin delta
41 64 - 07 18 10.74kHz ? bad value auto margin delta
42 64 - 07 0F 9.643kHz ? bad value auto margin delta
43 64 - 07 07 8.666kHz ? bad value auto margin delta
44 64 - 07 00 7.812kHz ? bad value auto margin delta
45 64 - 08 32 6.958kHz ? bad value auto margin delta
46 64 - 08 26 6.225kHz ? bad value auto margin delta
47 64 - 08 1B 5.554kHz ? bad value auto margin delta
48 64 - 08 12 5.004kHz ? bad value auto margin delta
49 64 - 08 0A 4.516kHz ? bad value auto margin delta
50 64 - 08 02 4.028kHz ? bad value auto margin delta
51 64 - 09 36 3.601kHz ? bad value auto margin delta
52 64 - 09 2A 3.234kHz ? bad value auto margin delta
53 64 - 09 1F 2.899kHz i stuck ir auto margin delta
54 64 - 09 15 2.593kHz ? bad value auto margin delta
55 64 - 09 0C 2.319kHz ? bad value auto margin delta
56 64 - 09 04 2.075kHz ? bad value auto margin delta
57 64 - 0A 3A 1.861kHz ? bad value auto margin delta
58 64 - 0A 2D 1.663kHz ? bad value auto margin delta
59 64 - 0A 22 1.495kHz ? bad value auto margin delta
60 64 - 0A 18 1.342kHz i stuck ir auto margin delta
61 64 - 0A 0F 1.205kHz ? bad value auto margin delta
62 64 - 0A 07 1.083kHz ? bad value auto margin delta
63 64 - 0A 00 976.0Hz ? bad value auto margin delta
64 64 - 0B 32 869.0Hz ? bad value auto margin delta
65 64 - 0B 26 778.0Hz i stuck ir auto margin delta
66 64 - 0B 1B 694.0Hz ? bad value auto margin delta
67 64 - 0B 12 625.0Hz ? bad value auto margin delta
68 64 - 0B 0A 564.0Hz ? bad value auto margin delta
69 64 - 0B 02 503.0Hz ? bad value auto margin delta
70 64 - 0B 00 488.0Hz {?} bad value auto margin delta
The first internal/external clock test resuts are:
The expect frequency was 500000Hz.
The actual frequency was 499872Hz.
The delta frequency was 128Hz.
The second internal/external clock test resuts are:
The expect frequency was 570312Hz.
The actual frequency was 569976Hz.
The delta frequency was 336Hz.
In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 12 bits.
The JTAG DR length was 2 bits.
The IR/DR scan-path tests used 70 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 570.3kHz as the highest frequency.
The IR/DR scan-path tests used 488.0Hz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
The frequency of the JTAG TCLKR input is measured as 488.0Hz.
The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 12 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Test 3 Word 3: scanned out 0xFE03E0E2 and scanned in 0x7E03E0E2.
Test 3 Word 4: scanned out 0xFE03E0E2 and scanned in 0xFE03E0E3.
Test 3 Word 9: scanned out 0xFE03E0E2 and scanned in 0xFE01E0E2.
Test 3 Word 11: scanned out 0xFE03E0E2 and scanned in 0xFE03F0E2.
Test 3 Word 15: scanned out 0xFE03E0E2 and scanned in 0xFE03E062.
Test 3 Word 21: scanned out 0xFE03E0E2 and scanned in 0xFE03E072.
Test 3 Word 29: scanned out 0xFE03E0E2 and scanned in 0xFF03E072.
Test 3 Word 30: scanned out 0xFE03E0E2 and scanned in 0xFE01E0E2.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 3, skipped: 0, failed: 1
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 2
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 3
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 4
Some of the values were corrupted - 19.8 percent.
The JTAG IR Integrity scan-test has failed.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Spectrum Digital XDS560V2 STM USB Emulator_0]
